Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

• US 10,396,214 B2
• Filed: 03/16/2018
• Issued: 08/27/2019
• Est. Priority Date: 07/15/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Hashemi, Pouya, Khakifirooz, Ali, Reznicek, Alexander
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US15/923,890
• Publication Number:
  US 20180212066A1
• Time in Patent Office: 529 Days
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET

Abstract

Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

Claims

1. A semiconductor structure comprising:

a vertical stack of semiconductor nanowires located atop a surface of a base layer, wherein the base layer has a concave upper surface located adjacent the vertical stack of semiconductor nanowires; and

a semiconductor material protruding portion located on a sidewall surface of each of the semiconductor nanowires.

2. The semiconductor structure of claim 1, wherein each of the semiconductor material protruding portions has a shape of a triangular and wherein a base of the triangular is present directly on the sidewall surface of each of the semiconductor nanowires of the vertical stack of semiconductor nanowires.

3. The semiconductor structure of claim 1, wherein each semiconductor nanowire of the vertical stack of semiconductor nanowires is vertically spaced apart from each other.

4. The semiconductor structure of claim 3, wherein each semiconductor material protruding portion is vertically spaced apart from each other.

5. The semiconductor structure of claim 1, wherein the base layer is composed of a semiconductor material, an insulator layer or a multilayered stack of a semiconductor material and an insulator layer.

6. The semiconductor structure of claim 1, further comprising a functional gate structure surrounding the vertical stack of semiconductor nanowires.

7. The semiconductor structure of claim 6, wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor material portion.

8. The semiconductor structure of claim 7, wherein the gate dielectric material portion is a continuous layer that contacts the entirety of each of the semiconductor material protruding portions, and is present between, and above, each of the semiconductor nanowires of the vertical stack of semiconductor nanowires.

9. The semiconductor structure of claim 1, wherein a bottommost semiconductor nanowire of the vertical stack of semiconductor nanowires is located directly on a non-recessed surface of the base layer.

10. The semiconductor structure of claim 1, wherein each semiconductor nanowire of the vertical stack of semiconductor nanowires comprises a same semiconductor material.

11. The semiconductor structure of claim 1, wherein each semiconductor nanowire of the vertical stack of semiconductor nanowires comprises a crystalline semiconductor material.

12. The semiconductor structure of claim 1, wherein each semiconductor material protruding portion composes a doped semiconductor material.

13. A semiconductor structure comprising:

a plurality of vertically stacked semiconductor nanowires laterally spaced apart from each other and located atop a surface of a base layer, wherein the base layer has a concave upper surface located adjacent each of the vertically stacked semiconductor nanowires; and

a semiconductor material protruding portion located on sidewall surfaces of each of the semiconductor nanowires of each of the plurality of vertically stacked semiconductor nanowires.

14. The semiconductor structure of claim 13, wherein each of the semiconductor material protruding portions has a shape of a triangular and wherein a base of the triangular is present directly on the sidewall surface of each of the least semiconductor nanowires.

15. The semiconductor structure of claim 13, wherein the semiconductor nanowires of each of the vertically stacked semiconductor nanowires are vertically spaced apart from each other.

16. The semiconductor structure of claim 13, further comprising a functional gate structure surrounding each of the vertically stacked semiconductor nanowires.

17. The semiconductor structure of claim 16, wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor material portion.

18. The semiconductor structure of claim 17, wherein the gate dielectric material portion is a continuous layer that contacts the entirety of each of the semiconductor material protruding portions, and is present between, and above, each of the semiconductor nanowires of the plurality of vertically stacked semiconductor nanowires.

19. A semiconductor structure comprising:

a vertical stack of semiconductor nanowires located atop a surface of a base layer;

a semiconductor material protruding portion located on a sidewall surface of each of the semiconductor nanowires; and

a functional gate structure surrounding the vertical stack of semiconductor nanowires, wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor material portion, and wherein the gate dielectric material portion is a continuous layer that contacts the entirety of each of the semiconductor material protruding portions, and is present between, and above, each of the semiconductor nanowires of the vertical stack of semiconductor nanowires.