Trench vertical JFET with improved threshold voltage control

• US 10,396,215 B2
• Filed: 09/09/2016
• Issued: 08/27/2019
• Est. Priority Date: 03/10/2015
• Status: Active Grant

• Current Assignee: United Silicon Carbide, Inc. (Qorvo, Inc.)
• Original Assignee: United Silicon Carbide, Inc. (Qorvo, Inc.)
• Inventors: Bhalla, Anup, Alexandrov, Peter
• Primary Examiner(s): Nicely, Joseph C.
• Assistant Examiner(s): Koo, Lamont B
• Application Number:
  US15/260,548
• Publication Number:
  US 20160380117A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.

Claims

1. A trench JFET, comprising:

a) a substrate comprising a backside drain region and a topside drift region, the backside drain region and the topside drift region being of a first doping type, wherein the first doping type is n-type;

b) mesas, the mesas extending from the topside drift region, wherein the mesas are separated by trenches cut into the topside drift region; and

c) in each mesa, a source region, a gate region, a vertical channel region, and a first mesa core region and a second mesa core region;

d) wherein the source region is of the first doping type and is located at the tops of the mesa;

e) wherein the gate region is of a second doping type and is located on the surfaces of the trenches, wherein the second doping type is p-type, and wherein the gate region abuts the source region;

f) wherein the first and second mesa core regions are of the first doping type, wherein the first mesa core region is located beneath source region and above the second mesa core, with the first mesa core region abutting the source region and the second mesa core region, and wherein the doping concentration at the center of the first mesa core region is at least ten times lower than that of the topside drift region;

g) wherein the vertical channel region is of the first doping type, where in the vertical channel region extends vertically substantially the height of the mesas and abuts the source region, and wherein the vertical channel region extends laterally to abut a portion of the gate region on the vertical wall of the trench and to abut a portion of the first mesa core region and a portion of the second mesa core region; and

h) wherein the peak doping concentration of the vertical channel region is at least ten times higher than the doping level of the center of the first mesa core region.

2. The trench JFET of claim 1, wherein the substrate further comprises silicon carbide.

3. The trench JFET of claim 1, wherein the substrate further comprises gallium nitride.

4. The trench JFET of claim 1, wherein the peak doping concentration of the vertical channel region is at least twenty times higher than the doping level of the center of the first mesa core region.

5. JFET of claim 1, wherein the peak doping concentration of the vertical channel region is at least fifty times higher than the doping level of the center of the first mesa core region.

6. The trench JFET of claim 1, further comprising an extension of the vertical channel region, wherein the extension of the vertical channel region extends past the bottom of the mesa and laterally beneath a portion of the gate region along the bottom of the trench, but does not extend fully across the bottom of the trench.

7. The trench JFET of claim 6, wherein the substrate further comprises silicon carbide.

8. The trench JFET of claim 6, wherein the substrate further comprises gallium nitride.

9. The trench JFET of claim 6, wherein a portion of the gate region on the bottom of the trench is doped more heavily than the portion of the gate region on the vertical wall of the trench.

10. The trench JFET of claim 1, wherein the source region extends the full width of the mesa.

11. The trench JFET of claim 1, wherein a gate-source junction extends to the sidewall of the mesa.

12. The trench JFET of claim 1, wherein a portion of the gate region on the bottom of the trench is doped more heavily than the portion of the gate region on the vertical wall of the trench.