GaN circuit drivers for GaN circuit loads

• US 10,396,579 B2
• Filed: 07/24/2017
• Issued: 08/27/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Cheng, Diana J.
• Application Number:
  US15/658,242
• Publication Number:
  US 20170324263A1
• Time in Patent Office: 764 Days
• Field of Search: 327108-112, 257 76, 257194, 257E29089, 257E27016, 257E29246
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Claims

1. An electronic circuit, comprising:

a substrate comprising GaN;

a first power supply node on the substrate;

an output node;

a signal node;

an output component on the substrate, wherein the output component is configured to selectively conduct current from the first power supply node to the output node based at least in part on a voltage at the signal node;

a resistive element; and

a capacitor coupled to the signal node through the resistive element, wherein the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

2. The electronic circuit of claim 1, wherein the output component comprises:

a first terminal coupled to the first power supply node;

a second terminal coupled to the output node, and

a third terminal coupled to the signal node, wherein a voltage at the third terminal controls an electrical conductivity between the first and second terminals of the output component.

3. The electronic circuit of claim 1, further comprising a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.

4. The electronic circuit of claim 1, wherein the capacitor causes the voltage at the signal node to be greater than the voltage of the first power supply node in response to the voltage at the output node increasing.

5. The electronic circuit of claim 1, further comprising first and second input nodes, wherein the voltage generated at the output node is a logic function of at least the voltages at the first and second input nodes.

6. The electronic circuit of claim 1, further comprising a pull-down device coupled to the signal node.

7. The electronic circuit of claim 6, further comprising:

a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node,

wherein the resistive element is coupled between the charging element and the pull-down device.

8. The electronic circuit of claim 1, further comprising:

an input node; and

a feedback element between the input node and the output node,

wherein the voltage generated at the output node is based on a voltage at the input node, and wherein the relationship between voltage at the input node and the voltage at the output node is hysteretic.

9. The electronic circuit of claim 1, further comprising a power switch formed on the substrate including a control gate coupled to the output node.

10. The electronic circuit of claim 1, wherein the electronic circuit comprises two inverters connected serially to form a non-inverting buffer circuit.

11. The electronic circuit of claim 1, further comprising an input node, wherein the voltage generated at the output node is a logic inversion of the input node.

23. The electronic circuit of claim 1, further comprising:

a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node, wherein the charging element comprises a selectively conductive charging switch configured to conduct while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.

12. An electronic component, comprising:

a package base;

at least one GaN-based die secured to the package base and including

an electronic circuit comprising;

a first power supply node on the GaN-based die;

an output node;

a signal node;

an output component on the GaN-based die, wherein the output component is configured to selectively conduct current from the first power supply node to the output node based at least in part on a voltage at the signal node;

a resistive element; and

a capacitor coupled to the signal node through the resistive element, wherein the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

13. The electronic component of claim 12, wherein the output component comprises:

a first terminal coupled to the first power supply node;

a second terminal coupled to the output node, and

a third terminal coupled to the signal node, wherein a voltage at the third terminal controls an electrical conductivity between the first and second terminals of the output component.

14. The electronic component of claim 12, wherein the electronic circuit further comprises a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.

15. The electronic component of claim 12, wherein the capacitor causes the voltage at the signal node to be greater than the voltage of the first power supply node in response to the voltage at the output node increasing.

16. The electronic component of claim 12, wherein the electronic circuit further comprises first and second input nodes, wherein the voltage generated at the output node is a logic function of at least the voltages at the first and second input nodes.

17. The electronic component of claim 12, further comprising a pull-down device coupled to the signal node.

18. The electronic component of claim 17, wherein the electronic circuit further comprises:

a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node; and

a resistive element coupled between the charging element and the pull-down device.

19. The electronic component of claim 12, wherein the electronic circuit further comprises:

an input node; and

a feedback element between the input node and the output node,

wherein the voltage generated at the output node is based on a voltage at the input node, and wherein the relationship between voltage at the input node and the voltage at the output node is hysteretic.

20. The electronic component of claim 12, wherein the electronic circuit further comprises a power switch formed on the GaN-based die including a control gate coupled to the output node.

21. The electronic component of claim 12, wherein the electronic circuit comprises two inverters connected serially to form a non-inverting buffer circuit.

22. The electronic component of claim 12, wherein the electronic circuit further comprises an input node, wherein the voltage generated at the output node is a logic inversion of the input node.

24. The electronic component of claim 12, wherein the electronic circuit further comprises:

a charging element configured to charge the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node, wherein the charging element comprises a selectively conductive charging switch configured to conduct while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.