Continuous time linear equalizer

• US 10,397,027 B2
• Filed: 09/26/2017
• Issued: 08/27/2019
• Est. Priority Date: 09/26/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Francese, Pier Andrea, Oezkaya, Ilter, Cevrero, Alessandro
• Primary Examiner(s): Tse, Young T
• Application Number:
  US15/715,205
• Publication Number:
  US 20190097845A1
• Time in Patent Office: 700 Days
• Field of Search: 375232, 375233, 375346, 375349, 375350, 4552511, 4552531, 4552532, 455338, 455339, 455340, 455341
• CPC Class Codes: H03F 2203/45022 One or more added resistors to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/34 DC amplifiers in which all stages are DC-coupled H03F3/45 takes precedence
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45224 Complementary Pl types having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45246 Folded cascode stages
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04L 2025/03541 Switching between domains, e.g. between time and frequency
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

Claims

1. A system comprising:

a first signal path comprising a high pass filter and a first controllable transconductance unit;

a second signal path comprising a second controllable transconductance unit; and

a summation node configured to receive complementary current summation signals of the first controllable transconductance unit and the second controllable transconductance unit, wherein the high pass filter comprises,

a first port configured to receive an input signal,

a second port coupled to a control port of the first controllable transconductance unit, and

a third port coupled to the summation node.

2. The system of claim 1, wherein the high pass filter is a first order high pass filter comprising a resistor and a capacitor.

3. The system of claim 2, wherein the capacitor is coupled between the first port and the second port of the high pass filter and the resistor is coupled between the second port and the third port of the high pass filter.

4. The system of claim 2, wherein the resistor is configured to provide a bias signal to the control port of the first controllable transconductance unit.

5. The system of claim 2, wherein the resistor is adjustable.

6. The system of claim 5, wherein the system is configured to provide a desired transfer function by adjusting a resistance of the adjustable resistor.

7. The system of claim 2, wherein the capacitor is adjustable.

8. The system of claim 7, wherein the system is configured to provide a desired transfer function by adjusting a capacitance of the adjustable capacitor.

9. The system of claim 1, wherein the second signal path is configured as low frequency path or all pass path.

10. The system of claim 1, wherein the first controllable transconductance unit comprises a p-type field effect transistor and the second controllable transconductance unit comprises an n-type field effect transistor.

11. The system of claim 10, wherein

a gate of the p-type field effect transistor is coupled to the second port of the high pass filter;

a source of the p-type field effect transistor is coupled to a supply voltage;

a drain of the p-type field effect transistor is coupled to the summation node;

a gate of the n-type field effect transistor is coupled to the second signal path;

a drain of the n-type field effect transistor is coupled to the summation node; and

a source of the n-type field effect transistor is coupled to ground.

12. The system of claim 1, wherein the first controllable transconductance unit comprises an n-type field effect transistor and the second controllable transconductance unit comprises a p-type field effect transistor.

13. The system of claim 12, wherein

a gate of the p-type field effect transistor is coupled to the second signal path;

a source of the p-type field effect transistor is coupled to a supply voltage;

a drain of the p-type field effect transistor is coupled to the summation node;

a gate of the n-type field effect transistor is coupled to the second port of the high pass filter;

a drain of the n-type field effect transistor is coupled to the summation node; and

a source of the n-type field effect transistor is coupled to ground.

14. The system of claim 1, wherein the system is configured such that

a transconductance of the first controllable transconductance unit is considerably greater than a transconductance of a resistor of the high pass filter;

and

the transconductance of the first controllable transconductance unit is substantially equal to a transconductance of the second controllable transconductance unit.

15. A method comprising:

receiving, by a summation node, complementary current summation signals of a first controllable transconductance unit and a second controllable transconductance unit,

wherein a first signal path comprises a high pass filter and the first controllable transconductance unit; and

wherein a second signal path comprises the second controllable transconductance unit; and

receiving, by the high pass filter, an input signal on a first port of the high pass filter,

wherein the high pass filter comprises a second port coupled to a control port of the first controllable transconductance unit and a third port coupled to the summation node.

16. The method of claim 15, wherein the high pass filter is a first order high pass filter comprising a resistor and a capacitor.

17. A system comprising:

a first signal path comprising a high pass filter and a first controllable transconductance unit;

a second signal path comprising a second controllable transconductance unit; and

a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit, wherein the high pass filter is a first order high pass filter comprising;

a resistor,

a capacitor,

a first port configured to receive an input signal,

a second port coupled to a control port of the first controllable transconductance unit, and

a third port coupled to the summation node,

wherein adjusting at least one of a capacitance of the capacitor or a resistance of the resistor controls a transfer function of the system.