Sensor array with edge pattern

• US 10,402,022 B2
• Filed: 03/01/2017
• Issued: 09/03/2019
• Est. Priority Date: 07/18/2012
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Badaye, Massoud, Vavaroutsos, Peter G, Ribeiro, Milton D. A., Hoshtanar, Oleksandr
• Primary Examiner(s): Patel, Premal R
• Application Number:
  US15/446,735
• Publication Number:
  US 20170262094A1
• Time in Patent Office: 916 Days
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/0448 Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality

Abstract

A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells.

Claims

1. A capacitive sensor array comprising:

a first unit cell formed by a first intersection of a first electrode and a second electrode; and

a second unit cell formed adjacent to the first unit cell and formed by a second intersection of the first electrode and a third electrode, wherein

a first trace of the first electrode in the first unit cell has a first edge length along the second electrode, and

a second trace of the first electrode in the second unit cell has a second edge length along the third electrode, the second edge length dissimilar from the first edge length along the second electrode.

2. The capacitive sensor array of claim 1, wherein the first unit cell is formed in an edge region of the capacitive sensor array.

3. The capacitive sensor array of claim 1, wherein the second unit cell is formed in a core region.

4. The capacitive sensor array of claim 1, wherein:

a third trace of the second electrode in the first unit cell has a third edge length along the first electrode; and

a fourth trace of the third electrode in the second unit cell has a fourth edge length along the second electrode.

5. The capacitive sensor array of claim 4, wherein the second edge length of the second trace and the fourth edge length of the fourth trace are similar.

6. The capacitive sensor array of claim 1, wherein a first mutual capacitance change by a presence of a conductive object in proximity to the first intersection is dissimilar from a second mutual capacitance change by the presence of the conductive object in proximity to the second intersection.

7. The capacitive sensor array of claim 1, wherein the first trace of the first electrode comprises at least one branch disposed within the first unit cell.

8. the capacitive sensor array of claim 1, further comprising a fifth trace parallel to the first trace and a connecting trace coupling the first trace and the fifth trace, the connective trace disposed within the first unit cell.

9. A system comprising:

a capacitive sensing circuit;

a first electrode coupled to the capacitive sensing circuit;

a second electrode coupled to the capacitive sensing circuit, the second electrode disposed perpendicular to the first electrode, the first and second electrodes forming a first unit cell at a first intersection between the first electrode and the second electrode; and

a third electrode coupled to the capacitive sensing circuit, the third electrode disposed perpendicular to the first electrode, the first and third electrodes forming a second unit cell at a second intersection between the first electrode and the third electrode, wherein;

the first electrode comprises a first trace having a first edge length along the second electrode within the first unit cell,

the first electrode comprises a second trace having a second edge length along the third electrode within the second unit cell, the first and second edge lengths dissimilar.

10. The system of claim 9, wherein the first unit cell is formed in an edge region of a capacitive sensor array comprising the first, second, and third electrodes.

11. The system of claim 9, wherein the second unit cell is formed in a core region.

12. The system of claim 9, wherein:

the second electrode comprises a third trace disposed within the first unit cell, the third trace having a third edge length along the first electrode; and

the third electrode comprises a fourth trace disposed within the second unit cell, the fourth trace having a fourth edge length along the second electrode.

13. The system of claim 12, wherein the second edge length of the second trace and the fourth edge length of the fourth trace are similar.

14. The system of claim 9, wherein the first trace of the first electrode comprises at least one branch disposed within the first unit cell.

15. The system of claim 9, wherein the first electrode comprises a fifth trace parallel to the first trace and a connecting trace coupling the first trace and the fifth trace, the connective trace disposed within the first unit cell.

16. A method comprising:

forming a first electrode disposed;

forming a second electrode perpendicular to the first electrode, wherein a first intersection between the first electrode and the second electrode identifies a first unit cell; and

forming a third electrode perpendicular to the first electrode, wherein a second intersection between the first electrode and the third electrode identifies a second unit cell, wherein

a first trace of the first electrode in the first unit cell has a first edge length along the second electrode, and

a second trace of the first electrode in the second unit cell has a second edge length along the third electrode, the second edge length dissimilar from the first edge length.

17. The method of claim 16, wherein the second electrode is forming within an edge region of a capacitive sensor array comprising the first, second, and third electrodes.

18. The method of claim 16, wherein the third electrode is formed within a core region and at least one edge region.

19. The method of claim 16, wherein:

a third trace of the second electrode in the first unit cell has a third edge length along the first electrode; and

a fourth trace of the third electrode in the second unit cell has a fourth edge length along the second electrode.

20. The method of claim 19, wherein the second edge length of the second trace and the fourth edge length of the fourth trace are similar.