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Detecting bus locking conditions and avoiding bus locks

  • US 10,402,218 B2
  • Filed: 08/30/2016
  • Issued: 09/03/2019
  • Est. Priority Date: 08/30/2016
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a register to store a bus-lock-disable bit; and

    an execution unit to execute instructions, wherein the execution unit is to;

    receive an instruction that includes a memory access request;

    determine that the memory access request requires acquiring a bus lock;

    responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system; and

    responsive to a determination that the memory access request originates from a virtual machine (VM) and that a bus-lock-exit bit is enabled within a virtual machine control structure (VMCS) associated with the VM, perform a VM exit of the VM to a virtual machine monitor (VMM), to preempt execution of the VM in lieu of acquiring the bus lock.

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