Detecting bus locking conditions and avoiding bus locks

• US 10,402,218 B2
• Filed: 08/30/2016
• Issued: 09/03/2019
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shanbhogue, Vedvyas, Neiger, Gilbert, Thiyagarajah, Arumugam
• Primary Examiner(s): Schell, Joseph O
• Application Number:
  US15/251,425
• Publication Number:
  US 20180060099A1
• Time in Patent Office: 1,099 Days
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/3027 where the computing system component is a bus
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/105 where the programme performs an input/output emulation function
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2009/45591 Monitoring or debugging support
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A processor may include a register to store a bus-lock-disable bit and an execution unit to execute instructions. The execution unit may receive an instruction that includes a memory access request. The execution may further determine that the memory access request requires acquiring a bus lock, and, responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system.

Claims

1. A processor comprising:

a register to store a bus-lock-disable bit; and

an execution unit to execute instructions, wherein the execution unit is to;

receive an instruction that includes a memory access request;

determine that the memory access request requires acquiring a bus lock;

responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system; and

responsive to a determination that the memory access request originates from a virtual machine (VM) and that a bus-lock-exit bit is enabled within a virtual machine control structure (VMCS) associated with the VM, perform a VM exit of the VM to a virtual machine monitor (VMM), to preempt execution of the VM in lieu of acquiring the bus lock.

2. The processor of claim 1, wherein the fault is a general protection fault.

3. The processor of claim 1, wherein the register is a model-specific register.

4. The processor of claim 1, wherein the execution unit is further to terminate execution of the instruction responsive to detecting that the bus-lock-disable bit is enabled.

5. The processor of claim 1, wherein the execution unit is further to, responsive to the fault, execute a fault handler of the operating system to:

disable memory accesses by an agent other than the operating system; and

emulate execution of the instruction without requiring a bus lock.

6. The processor of claim 1, wherein the memory access request comprises a locked operation to uncacheable memory.

7. The processor of claim 1, wherein the memory access request comprises a locked operation that spans multiple cache lines.

8. The processor of claim 1, wherein the memory access request comprises a page-walk from a page table in uncacheable memory.

9. A system on a chip (SoC) comprising:

a memory to store a virtual machine control structure (VMCS); and

a core coupled to the memory, wherein the core is to execute instructions of a virtual machine (VM), and wherein the core is to execute a virtual machine monitor (VMM) to control entry into and exit from the virtual machine;

wherein the core is further to;

execute VM extensions execution control instructions to detect a condition with reference to execution of the virtual machine that requires acquiring a bus lock; and

responsive to detecting that a bus-lock-exiting bit is enabled by a field of the VMCS, perform a VM exit to the VMM to preempt execution of the virtual machine in lieu of acquiring the bus lock.

10. The SoC of claim 9, wherein the condition comprises a memory access request of the virtual machine that requires acquiring the bus lock.

11. The SoC of claim 9, wherein the core is further to store, in the VMCS, acquisition of a bus lock as a reason for the VM exit.

12. The SoC of claim 9, wherein the VM exit is prioritized over signaling a fault or exception to an operating system of the virtual machine.

13. The SoC of claim 9, wherein the core is further to:

retrieve, from a bus lock policy bit of the VMCS, a bus lock exit policy defining a threshold number of allowed bus locks; and

perform the VM exit of the virtual machine to the VMM responsive to receiving a request for a bus lock that exceeds the threshold number of allowed bus locks.

14. A system comprising:

a memory to store a virtual machine control structure (VMCS); and

a processor coupled to the memory, wherein the processor is to execute instructions of a virtual machine (VM), and wherein the processor is to execute a virtual machine monitor (VMM) to manage the virtual machine;

wherein the processor is further to;

execute VM extensions execution control instructions to detect a memory access in response to executing an instruction within the virtual machine that requires acquiring a bus lock; and

responsive to detecting that a bus-lock-exiting bit is enabled within the VMCS, perform a VM exit to the VMM to preempt execution of the virtual machine in lieu of acquiring the bus lock.

15. The system of claim 14, wherein the processor is further to store, in the VMCS, acquisition of a bus lock as a reason for the VM exit.

16. The system of claim 14, wherein the VM exit is prioritized over signaling a fault or exception to an operating system of the virtual machine.

17. The system of claim 14, wherein the processor is further to:

retrieve, from a bus lock policy bit of the VMCS, a bus lock exit policy defining a threshold number of allowed bus locks; and

perform the VM exit of the virtual machine to the VMM responsive to receiving a request for a bus lock that exceeds the threshold number of allowed bus locks.

18. A method comprising:

receiving, by execution unit of a processor, an instruction that generates a memory access request;

determining, by the execution unit, that the memory access request requires acquiring a bus lock;

responsive to determining that a bus-lock-disable bit is enabled within a register, transmitting, by the execution unit, a fault to an operating system; and

responsive to determining that the memory access request originates from a virtual machine (VM) and that a bus-lock-exit bit is enabled within a virtual machine control structure (VMCS) associated with the VM, performing a VM exit of the virtual machine to a virtual machine monitor (VMM), to preempt execution of the VM in lieu of acquiring the bus lock.

19. The method of claim 18, wherein the fault is a general protection fault.

20. The method of claim 18, further comprising terminating, by the execution unit, execution of the instruction responsive to detecting that the bus-lock-disable bit is enabled.

21. The method of claim 18, further comprising, responsive to the fault, executing a fault handler to:

disable memory accesses by an agent other than the operating system; and

emulate execution of the instruction without requiring a bus lock.

22. The method of claim 18, further comprising storing, in the VMCS, acquisition of a bus lock as a reason for the VM exit.

23. The method of claim 18, wherein signaling a segmentation fault or a paging-related fault to an operating system of the virtual machine is prioritized over performing the VM exit.

24. The method of claim 18, further comprising:

receiving, from the VMM, a bus lock exit policy defining a threshold number of allowed bus locks per second; and

performing the VM exit of the virtual machine to the VMM responsive to detecting more bus locks than the threshold number of bus locks allowed per second.