Validation of a symbol response memory

• US 10,402,265 B2
• Filed: 07/09/2018
• Issued: 09/03/2019
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Natural Intelligence Systems, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noyes, Harold B, Brown, David R., Glendenning, Paul
• Primary Examiner(s): Rizk, Samir W
• Application Number:
  US16/030,479
• Publication Number:
  US 20180322006A1
• Time in Patent Office: 421 Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

Claims

1. A system, comprising:

a host processor configured to transmit instructions corresponding to data to be analyzed; and

a state machine engine coupled to the host processor and configured to be programmed via the instructions, wherein the state machine engine comprises;

a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of rows, wherein each row of the plurality of rows comprises a plurality of configurable elements, wherein each configurable element of the plurality of configurable elements comprises a data analysis element comprising a memory component programmed with configuration data comprising a portion of the instructions, wherein the data analysis element is configured to analyze at least a portion of the data based on the configuration data and to output a result; and

an error detection engine (EDE) configured to perform integrity validation of the configuration data.

2. The system of claim 1, wherein the EDE is configured to utilize one or more cyclic redundancy checks (CRC) to perform the integrity validation of the configuration data.

3. The system of claim 2, wherein the EDE comprises a processor configured to calculate one or more initial CRC values based on the configuration data.

4. The system of claim 3, wherein the EDE comprises a memory configured to store the one or more initial CRC values.

5. The system of claim 4, wherein the EDE is configured to compare the one or more initial CRC values against one or more additionally calculated CRC values and output a signal to the host processor when the one or more additionally calculated CRC values differ from the one or more initial CRC values.

6. The system of claim 2, wherein the host processor is configured to calculate one or more initial CRC values based on the configuration data and transmit the one or more initial CRC values to the state machine engine as a portion of the instructions.

7. The system of claim 6, wherein the EDE comprises a memory configured to store the one or more initial CRC values.

8. The system of claim 7, wherein the EDE is configured to compare the one or more initial CRC values against one or more additionally calculated CRC values and output a signal to the host processor via the state machine engine when the one or more additionally calculated CRC values differ from the one or more initial CRC values.

9. The system of claim 8, wherein the host processor, based on the signal, is configured to retransmit the instructions to the state machine engine to reprogram the memory component of the data analysis element of each of the plurality of configuration elements with the configuration data.

10. The system of claim 1, wherein the EDE is configured to perform the integrity validation at a block level comprising at least one block of the plurality of blocks, at a core level including the plurality of blocks, or both.

11. The system of claim 1, wherein the memory component comprises a symbol response memory (SRM) including a plurality of memory cells that each store a high value or a low value based on the configuration data.

12. A system, comprising:

a host processor configured to transmit instructions corresponding to data to be analyzed;

a memory coupled to the host processor and configured to store the data to be analyzed; and

a state machine engine coupled to the host processor and to the memory, wherein the state machine engine is configured to;

receive and be programmed by the instructions from the host processor;

receive the data to be analyzed from the memory; and

transmit a result of an analysis of the data by the state machine engine to the host processor, wherein the state machine engine comprises;

a plurality of configurable elements, wherein each configurable element of the plurality of configurable elements is configured to be programmed via configuration data received as a portion of the instructions and to selectively output a result as a portion of the result of the analysis; and

an error detection engine (EDE) configured to validate an integrity of the configuration data.

13. The system of claim 12, wherein the state machine engine comprises a finite state machine lattice, wherein the finite state machine lattice comprises the plurality of configurable elements and the EDE.

14. The system of claim 13, wherein the finite state machine lattice comprises a programming interface configured to:

receive the configuration data from the host processor;

program each of the plurality of configurable elements with the configuration data; and

send the configuration data to the EDE to calculate one or more initial cyclic redundancy check (CRC) values based on the configuration data each time the configuration data is received from the host processor.

15. The system of claim 12, wherein the EDE is configured to utilize a cyclic redundancy check (CRC) to at least partially validate the integrity of the configuration data by receiving the configuration data from the host processor, calculating one or more initial CRC values based on the configuration data, receiving a request from the host processor to validate the integrity of the configuration data, calculating one or more subsequent CRC values based on configuration data retrieved from the host processor at a later time, and determining whether the one or more initial CRC values differ from the one or more subsequent CRC values.

16. The system of claim 15, wherein the EDE is configured to output a signal indicative of an error in the configuration data to the host processor when the one or more initial CRC values differ from the one or more subsequent CRC values.

17. The system of claim 16, wherein the host processor is configured to reprogram each of the plurality of configurable elements based on the signal.

18. The system of claim 12, wherein the EDE is configured to at least partially validate the integrity of the configuration data by:

receiving one or more initial cyclic redundancy check (CRC) values from the host processor;

receiving an instruction from the host processor to validate the integrity of the configuration data;

calculating one or more subsequent CRC values based on the configuration data retrieved at a later time; and

determining whether the one or more initial CRC values differs from the one or more subsequent CRC values.

19. The system of claim 12, wherein the EDE is configured to at least partially validate the integrity of the configuration data by determining whether an initial cyclic redundancy check (CRC) value generated based on the configuration data at a first time differs from a subsequent CRC value generated at a second time.

20. A system, comprising:

a host processor configured to transmit instructions corresponding to data to be analyzed; and

a state machine engine coupled to the host processor and configured to be programmed via the instructions, wherein the state machine engine comprises;

a finite state machine lattice comprising;

a plurality of blocks, each block of the plurality of blocks comprising;

a plurality of rows, each row of the plurality of rows comprising;

 

a plurality of configurable elements, wherein each configurable element of the plurality of configurable elements comprises a memory (SRM) that utilizes configuration data comprising a part of the instructions to analyze at least a portion of the data and to selectively output a result; and

an error detection engine (EDE) configured to at least partially validate an integrity of the configuration data by determining whether an initial cyclic redundancy check (CRC) value generated based on the configuration data at a first time differs from a subsequent CRC value generated at a second time.

21. The system of claim 20, wherein the EDE is configured to output a signal indicative of an error to the host processor when the initial CRC value differs from the subsequent CRC value.

22. The system of claim 21, wherein the host processor is configured to reprogram each of the plurality of configurable elements based on the signal.