Redundant array of independent disks in a direct-mapped flash storage system

• US 10,402,266 B1
• Filed: 07/31/2017
• Issued: 09/03/2019
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Kirkpatrick, Peter E., Karr, Ronald
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/665,128
• Time in Patent Office: 764 Days
• Field of Search: 714758, 714761, 714757
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In one implementation, storage system includes embedded storage devices, where each embedded storage device includes a direct-mapped solid state drive (SSD) storage portion and storage system controllers. The storage system controllers may be operatively coupled to the embedded storage devices via a bus. The storage system controllers may receive data to be written to the plurality embedded storage devices, select a plurality of available allocation units from the direct-mapped SSD storage portions of the plurality of embedded storage devices, respectively, and calculate a verification signature corresponding to the data. The storage system controllers may also write the data and the verification signature to a first subset of the plurality of available allocation units, calculate an erasure code corresponding to the data and the verification signature, and write the erasure code to a second subset of allocation units.

Claims

1. A storage system comprising:

a plurality of three or more embedded storage devices, wherein each embedded storage device of the plurality of embedded storage devices comprises a direct-mapped solid state drive (SSD) storage portion; and

a plurality of storage system controllers, operatively coupled to the plurality embedded storage devices via a bus, the plurality of storage system controllers to;

receive data to be written to the plurality of three or more embedded storage devices;

select a plurality of available allocation units from three or more of the direct-mapped SSD storage portions of the plurality of embedded storage devices;

calculate a plurality of verification signatures, each corresponding to a separate one of the plurality of available allocation units;

write the data and the plurality of verification signatures to a first subset of the plurality of available allocation units;

calculate at least two erasure codes corresponding to the data and the verification signature; and

write the at least two erasure codes to a second subset of allocation units.

2. The storage system of claim 1, wherein the plurality of storage system controllers is further to:

detect that an allocation unit of the first subset of the plurality of available allocation units has failed or has been corrupted by comparing the data to the plurality of verification signatures; and

in response to the detecting, recover a portion of the data from the allocation unit based on the data written to the first subset of the plurality of available allocation units and the erasure codes written to the second subset of allocation units.

3. The storage system of claim 2, wherein the plurality of storage system controllers is further to:

determine that a device controller of an embedded storage device corresponding to the allocation unit did not correct a failure or corruption of the allocation unit; and

after determining that the device controller did not correct the failure or corruption, recover the portion of the data.

4. The storage system of claim 2, wherein to write the at least two erasure codes the plurality of storage system controllers is further to:

write a first erasure code of the at least two erasure codes to a first allocation unit of the subset of the plurality of available allocation units; and

write a second erasure code of the at least two erasure codes to a second allocation unit of the subset of the plurality of available allocation units in parallel with the first portion.

5. The storage system of claim 1, wherein the plurality of storage system controllers is to map the plurality of allocation units to erase blocks as directly addressable storage, and wherein the plurality of allocation units are categorized as available for use, in use, or unusable.

6. The storage system of claim 1, further comprising a non-volatile random-access memory (NVRAM) portion to journal the data, wherein the direct-mapped SSD portion and the NVRAM portion are separately addressable, and wherein the NVRAM portion is smaller than the direct-mapped SSD portion.

7. The storage system of claim 1, wherein the plurality of storage system controllers is further to:

calculate a plurality of additional erasure codes, each corresponding to a separate one of the plurality of available allocation units; and

write each of the plurality of additional erasure codes to a corresponding allocation unit.

8. A storage system comprising:

a plurality of embedded storage devices, wherein each embedded storage device of the plurality of embedded storage devices comprises a direct-mapped solid state drive (SSD) storage portion; and

a plurality of storage system controllers, operatively coupled to the plurality embedded storage devices via a bus, the plurality of storage system controllers to;

receive data to be written to the plurality embedded storage devices;

select a plurality of available allocation units from the direct-mapped SSD storage portions of the plurality of embedded storage devices;

calculate a verification signature corresponding to the data;

write the data and the verification signature to a first subset of the plurality of available allocation units;

calculate an erasure code corresponding to the data and the verification signature; and

write the erasure code to a second subset of allocation units.

9. The storage system of claim 8, wherein storage system controller is further to:

detect that an allocation unit of the first subset of the available allocation units has failed or has been corrupted by comparing the data to the verification signature; and

in response to the detecting, recover a portion of the data from the allocation unit based on the data written to the first subset of the available allocation units and the erasure code written to the second subset of allocation units.

10. The storage system of claim 9, wherein the storage system controller is further to:

determine that a device controller of an embedded storage device corresponding to the allocation unit did not correct a failure or corruption of the allocation unit; and

after determining that the device controller did not correct the failure or corruption, recover the portion of the data.

11. The storage system of claim 9, wherein the erasure code comprises a first portion and a second portion, and wherein to write the erasure code the storage system controller is further to:

write the first portion to a first allocation unit of the subset of the plurality of available allocation units; and

write the second portion to a second allocation unit of the subset of the plurality of available allocation units in parallel with the first portion.

12. The storage system of claim 8, wherein the storage system controller is to map the plurality of allocation units to erase blocks as directly addressable storage, and wherein the plurality of allocation units are categorized as available for use, in use, or unusable.

13. The storage system of claim 8, further comprising a non-volatile random-access memory (NVRAM) portion to journal the data, wherein the direct-mapped SSD portion and the NVRAM portion are separately addressable, and wherein the NVRAM portion is smaller than the direct-mapped SSD portion.

14. The storage system of claim 8, wherein the plurality of storage system controllers is further to:

calculate a plurality of additional erasure codes, each corresponding to a separate one of the plurality of available allocation units; and

write each of the plurality of additional erasure codes to a corresponding allocation unit.

15. A method comprising:

receiving data to be written to a plurality of embedded storage devices;

selecting a plurality of available allocation units from a plurality of direct-mapped solid-state-drive storage portions of the plurality of embedded storage devices;

writing the data and a verification signature corresponding to the data to a first subset of the plurality of available allocation units;

calculating an erasure code corresponding to the data and the verification signature; and

writing the erasure code to a second subset of allocation units.

16. The method of claim 15, further comprising:

detecting that an allocation unit of the first subset of the available allocation units has failed or has been corrupted by comparing the data to the verification signature; and

in response to the detecting, recovering a portion of the data from the allocation unit based on the data written to the first subset of the available allocation units and the erasure code.

17. The method of claim 16, further comprising:

determining that a device controller of an embedded storage device corresponding to the allocation unit did not correct a failure or corruption of the allocation unit; and

after determining that the device controller did not correct the failure or corruption, recovering the portion of the data.

18. The method of claim 16, wherein the erasure code comprises a first portion and a second portion, and wherein to write the erasure code the method further comprises:

writing the first portion to a first allocation unit of the subset of the plurality of available allocation units; and

writing the second portion to a second allocation unit of the subset of the plurality of available allocation units in parallel with the first portion.

19. The method of claim 15, further comprising journaling the data in a non-volatile random-access memory (NVRAM) portion, wherein the direct-mapped SSD portion and the NVRAM portion are separately addressable, and wherein the NVRAM portion is smaller than the direct-mapped SSD portion.

20. The method of claim 19, wherein the NVRAM portion comprises:

a random access memory (RAM) device;

an energy storing device; and

a processing device.