Memory array page table walk
First Claim
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1. An apparatus, comprising:
- an array comprising memory cells arranged in rows coupled by access lines and columns coupled by sense lines;
sensing circuitry coupled to the array and comprising;
sense amplifiers each corresponding to different sense lines; and
compute components each corresponding to the different sense lines; and
a memory controller coupled to the array, wherein the memory controller is configured to operate the sensing circuitry to;
cause storing of a page table in the array;
determine, in the array and without sending data outside the array, a physical address of a portion of data by accessing the page table; and
cause storing of the portion of data in a buffer.
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Abstract
An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.
320 Citations
24 Claims
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1. An apparatus, comprising:
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an array comprising memory cells arranged in rows coupled by access lines and columns coupled by sense lines; sensing circuitry coupled to the array and comprising;
sense amplifiers each corresponding to different sense lines; and
compute components each corresponding to the different sense lines; anda memory controller coupled to the array, wherein the memory controller is configured to operate the sensing circuitry to; cause storing of a page table in the array; determine, in the array and without sending data outside the array, a physical address of a portion of data by accessing the page table; and cause storing of the portion of data in a buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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searching for a physical address corresponding to a virtual address in a lookaside translation buffer (TLB); determining that the virtual address is not located in the TLB; performing a page table walk in a memory array comprising memory cells arranged in rows coupled by access lines and columns coupled by sense lines, wherein the page table walk is performed; independent of intermediate page table walk instructions from a host and without sending data outside the memory array; and by performing each of a number of logical operations using compute components of sensing circuitry of the memory array on a sense line by sense line bases, wherein the compute components correspond to different respective sense lines; and locating the physical address based on the page table walk. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An apparatus, comprising:
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an array of memory cells configured to store a page table and arranged in rows coupled by access lines and columns coupled by sense lines; sensing circuitry coupled to the array and comprising;
sense amplifiers each corresponding to different sense lines; and
compute components each corresponding to the different sense lines; anda controller coupled to the array, wherein the controller is configured to operate the sensing circuitry to; search for an address in a translation lookaside buffer (TLB), wherein the address is associated with a portion of data; in response to the address being absent from the TLB, perform a walk through the page table without sending data outside the array; determine a physical address of the portion of data based on the page table walk; and cause storing of the portion of data in the TLB. - View Dependent Claims (20, 21)
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22. A method, comprising:
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performing a page table walk on a page table stored in a memory array to determine a physical address associated with a portion of data in response to determining that a virtual address associated with the portion of data is not located in a translation lookaside buffer (TLB), wherein the memory array comprises memory cells arranged in rows coupled by access lines and columns coupled by sense lines; wherein performing the page table walk comprises; resolving page table levels simultaneously; using compute components of the sensing circuitry to perform each of a number of logical operations on a sense line by sense line bases, wherein the compute components correspond to different respective sense lines; and without sending data outside the memory array. - View Dependent Claims (23, 24)
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Specification