Method and system for using feedback information for selecting a routing bus for a memory transaction
First Claim
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1. A system on chip (SOC), comprising:
- a memory subsystem;
first and second requestors for access to the memory subsystem;
a router coupled to the first and second requestors;
first and second memory arbiters;
a first routing bus coupling the router to the first memory arbiter; and
a second routing bus coupling the router to the second memory arbiter;
wherein the first memory arbiter is operable to generate feedback information to the router indicating a usage capacity condition of the first memory arbiter, andwherein the router selects either the first routing bus or second routing bus for a memory transaction based on the generated feedback information.
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Abstract
A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).
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Citations
16 Claims
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1. A system on chip (SOC), comprising:
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a memory subsystem; first and second requestors for access to the memory subsystem; a router coupled to the first and second requestors; first and second memory arbiters; a first routing bus coupling the router to the first memory arbiter; and a second routing bus coupling the router to the second memory arbiter; wherein the first memory arbiter is operable to generate feedback information to the router indicating a usage capacity condition of the first memory arbiter, and wherein the router selects either the first routing bus or second routing bus for a memory transaction based on the generated feedback information. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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receiving feedback information indicative of an overload condition from an arbiter; generating the feedback information for the arbiter by comparing a number of outstanding transactions to a threshold; setting a bit to a first state if the number of outstanding transactions exceeds the threshold and to a second state if the number of outstanding transactions is less the threshold; deprioritizing a routing bus based on the received feedback information; and selecting a routing bus to use to send a transaction across a system-on-chip (SOC). - View Dependent Claims (11)
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9. A method, comprising:
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receiving feedback information indicative of an overload condition from an arbiter; deprioritizing a first routing bus from a plurality of routing buses based on the received feedback information; and selecting a second routing bus from the plurality of routing buses to use to send a transaction across a system-on-chip (SOC). - View Dependent Claims (10, 12, 13)
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14. A system on chip (SOC), comprising:
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a multi-channel memory subsystem comprising a separate memory bus for each memory channel in the multi-channel memory subsystem; first and second processors configured to issue memory transactions for access to the memory subsystem; a router coupled to the first and second processors; first and second memory arbiters; and a first routing bus coupling the router to the first memory arbiter; a second routing bus coupling the router to the second memory arbiter; wherein the first memory arbiter generates an overload bit indicating whether the first memory arbiter has a level of outstanding memory transactions that exceeds a threshold. - View Dependent Claims (15, 16)
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Specification