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Method and system for using feedback information for selecting a routing bus for a memory transaction

  • US 10,402,348 B2
  • Filed: 11/25/2013
  • Issued: 09/03/2019
  • Est. Priority Date: 04/12/2013
  • Status: Active Grant
First Claim
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1. A system on chip (SOC), comprising:

  • a memory subsystem;

    first and second requestors for access to the memory subsystem;

    a router coupled to the first and second requestors;

    first and second memory arbiters;

    a first routing bus coupling the router to the first memory arbiter; and

    a second routing bus coupling the router to the second memory arbiter;

    wherein the first memory arbiter is operable to generate feedback information to the router indicating a usage capacity condition of the first memory arbiter, andwherein the router selects either the first routing bus or second routing bus for a memory transaction based on the generated feedback information.

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