Method and system for using feedback information for selecting a routing bus for a memory transaction

• US 10,402,348 B2
• Filed: 11/25/2013
• Issued: 09/03/2019
• Est. Priority Date: 04/12/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Aldis, James Philip, Mestrallet, Philippe Yvan
• Primary Examiner(s): Phan, Raymond N
• Application Number:
  US14/089,314
• Publication Number:
  US 20140310444A1
• Time in Patent Office: 2,108 Days
• Field of Search: 710305-317, 710104-110, 710111-119, 709238-244
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).

Claims

1. A system on chip (SOC), comprising:

a memory subsystem;

first and second requestors for access to the memory subsystem;

a router coupled to the first and second requestors;

first and second memory arbiters;

a first routing bus coupling the router to the first memory arbiter; and

a second routing bus coupling the router to the second memory arbiter;

wherein the first memory arbiter is operable to generate feedback information to the router indicating a usage capacity condition of the first memory arbiter, and

wherein the router selects either the first routing bus or second routing bus for a memory transaction based on the generated feedback information.

2. The SOC of claim 1, wherein the feedback information corresponding to the first arbiter includes a bit for which one state specifies that the router has less than a threshold number of outstanding memory transactions and another state specifies that the router has the threshold number or greater of outstanding memory transactions.

3. The SOC of claim 1, wherein the router selects either the first routing bus or second routing bus for a memory transaction based on a round robin basis and the feedback information.

4. The SOC of claim 1 wherein the memory subsystem includes a multi-channel memory subsystem comprising a separate memory bus for each memory channel in the multi-channel memory subsystem.

5. The SOC of claim 1, wherein the router selects between the first and second routing buses for a memory transaction based on a round robin, least-recently-served or first-in-first-out basis from among the arbiters coupled to that router and the feedback information.

6. The SOC of claim 3, wherein the router deprioritizes the first router with respect to the second router when the generated feedback information indicates an overload capacity condition.

7. The SOC of claim 3, wherein the router prioritizes the first router when the generated feedback information does not indicate an overload capacity condition.

8. A method, comprising:

receiving feedback information indicative of an overload condition from an arbiter;

generating the feedback information for the arbiter by comparing a number of outstanding transactions to a threshold;

setting a bit to a first state if the number of outstanding transactions exceeds the threshold and to a second state if the number of outstanding transactions is less the threshold;

deprioritizing a routing bus based on the received feedback information; and

selecting a routing bus to use to send a transaction across a system-on-chip (SOC).

11. The method of claim 8 wherein the transaction is a memory transaction.

9. A method, comprising:

receiving feedback information indicative of an overload condition from an arbiter;

deprioritizing a first routing bus from a plurality of routing buses based on the received feedback information; and

selecting a second routing bus from the plurality of routing buses to use to send a transaction across a system-on-chip (SOC).

10. The method of claim 9 further comprising generating the feedback information by comparing a number of outstanding transactions to a threshold.

12. The method of claim 9 further comprising deprioritizing multiple routing buses based on the received feedback information.

13. The method of claim 9, wherein deprioritizing a first routing bus comprises moving an identifier of the first routing bus within a priority list.

14. A system on chip (SOC), comprising:

a multi-channel memory subsystem comprising a separate memory bus for each memory channel in the multi-channel memory subsystem;

first and second processors configured to issue memory transactions for access to the memory subsystem;

a router coupled to the first and second processors;

first and second memory arbiters; and

a first routing bus coupling the router to the first memory arbiter;

a second routing bus coupling the router to the second memory arbiter;

wherein the first memory arbiter generates an overload bit indicating whether the first memory arbiter has a level of outstanding memory transactions that exceeds a threshold.

15. The SOC of claim 14 wherein the overload bit from the first memory arbiter is used by the router to deprioritize the first routing bus for a memory transaction.

16. The SOC of claim 15 wherein the router deprioritizes the first routing bus within a priority list when the overload bit from the first memory arbiter indicates that the first memory arbiter has a level of outstanding memory transaction that exceeds a threshold.