Interface components

• US 10,402,351 B2
• Filed: 08/23/2018
• Issued: 09/03/2019
• Est. Priority Date: 07/06/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rowley, Matthew D., Castro, Peter R.
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US16/110,171
• Publication Number:
  US 20190012280A1
• Time in Patent Office: 376 Days
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Claims

1. An apparatus, comprising:

a controller configured to be coupled to a host;

a first interface component coupled to the controller and to a first memory device; and

a second interface component coupled to a second memory device and coupled in series with the first interface component;

wherein the first interface component is configured to;

receive a packet from the controller;

determine whether the packet is intended for the first interface component; and

send the packet to the second interface component in response to determining that the packet is not intended for the first interface component;

wherein the second interface component is configured to;

receive the packet sent thereto from the first interface component; and

depacketize the packet.

2. The apparatus of claim 1, wherein the first and second interface components are application specific integrated circuits.

3. The apparatus of claim 1, wherein the first interface component is configured to serialize outputs to the controller and deserialize inputs from the controller.

4. The apparatus of claim 1, wherein the first interface component is configured to packetize an input from the first memory device and to send the packetized input to the controller.

5. The apparatus of claim 1, wherein the first interface component is configured to depacketize an input from the controller in response to determining that the packet is intended for the first interface component and to determine from the depacketized input an operation to be performed on the first memory device.

6. The apparatus of claim 1, wherein the first interface component comprises a packetizer/depacketizer and a controller configured to control the packetizer/depacketizer.

7. The apparatus of claim 1, wherein the first interface component comprises:

a first interface coupled to the controller and a second interface coupled to the the first memory device; and

an interface controller associated with the first interface.

8. An apparatus, comprising:

a first controller; and

a plurality of respective interface components, wherein

the respective interface components are coupled in parallel to the first controller through respective channels;

each respective interface component is coupled to a respective plurality of memory devices; and

each respective interface component comprises;

a second controller;

an interface configured to deserialize a series of packets received from the first controller; and

a packetizer/depacketizer configured to depacketize the packets of the deserialized series of packets.

9. The apparatus of claim 8, wherein each respective interface component further comprises at least one of a memory-management engine, a wear-leveling engine, and an error-correction engine coupled to the second controller.

10. The apparatus of claim 8, wherein each respective interface component further comprises:

an interface controller corresponding to the interface.

11. The apparatus of claim 8, wherein the second controller is to control at least one of error correction, access to a memory device of the respective plurality of memory devices, an overprovisioning operation on a memory device of the respective plurality of memory devices, and a garbage collection operation on a memory device of the respective plurality of memory devices.

12. The apparatus of claim 8, wherein the interface comprises an interface selected from the group comprising a serial interface, a SerDes interface, an LVDS interface, and a serialized ONFI interface.

13. A method of operating an apparatus, comprising:

receiving, from a controller, a packet at a first interface component that is coupled to a first memory device;

determining, by the first interface component, whether the packet is intended for the first interface component;

sending the packet to a second interface component, coupled to a second memory device and coupled in series with the first interface component, in response to determining that the packet is not intended for the first interface component; and

depacketizing the packet using the second interface component.

14. The method of claim 13, further comprising performing an operation on the second memory device in response to an instruction in the depacketized packet.

15. The method of claim 14, wherein performing the operation on the second memory device comprises reading data from a location in the second memory device specified in the depacketized packet.

16. The method of claim 15, further comprising packetizing the read data using the second interface component and sending the packetized read data to the controller through the first interface component from the second interface component.

17. The method of claim 16, further comprising using the second interface component to serialize the packetized read data before sending the packetized read data to the controller.

18. The method of claim 14, wherein performing the operation on the second memory device comprises writing data contained in the depacketized packet to a location in the second memory device specified in the depacketized packet.

19. The method of claim 13, further comprising using the second interface component to deserialize the packet before depacketizing the packet.

20. The method of claim 13, further comprising:

depacketizing the packet using the first interface component in response to determining that the packet is intended for the first interface component; and

performing an operation on the first memory device in response to an instruction in the depacketized packet depacketized by the first interface component.