Method, apparatus, communication equipment and storage media for determining link delay

• US 10,402,354 B2
• Filed: 04/14/2015
• Issued: 09/03/2019
• Est. Priority Date: 10/14/2014
• Status: Active Grant

• Current Assignee: Sanechips Technology Co., Ltd. (ZTE Corporation)
• Original Assignee: Sanechips Technology Co., Ltd. (ZTE Corporation)
• Inventors: Yang, Lining, Hao, Peng, Huang, Can
• Primary Examiner(s): Oberly, Eric T
• Application Number:
  US15/519,275
• Publication Number:
  US 20170235689A1
• Time in Patent Office: 1,603 Days
• CPC Class Codes: G06F 11/3027 where the computing system component is a bus
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4278 using an embedded synchronisation

Abstract

The disclosure provides a method for determining link delay. The method includes: according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and, according to the second LMFC, writing respectively the data of each data lane into a corresponding buffer; and according to a SYSREF signal and a preset LMFC interval, generating a third LMFC, and, according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer. The period of the second LMFC is the same as the period of the third LMFC. The disclosure also provides an apparatus, a communication device and a storage medium for implementing the method.

Claims

1. A method for determining link delay, comprising:

according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and according to the second LMFC, writing respectively data of each data lane into a corresponding buffer; and

according to a system reference (SYSREF) signal and a preset LMFC interval, generating a third LMFC, and according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer, wherein

a period of the second LMFC is the same as a period of the third LMFC;

wherein the period of the second LMFC corresponding to each data lane obtained after the frequency division is greater than a data transmission delay difference corresponding to a data lane having the maximum data transmission delay in all the data lanes before the frequency division.

2. The method according to claim 1, wherein, according to the preset frequency division multiple, performing the frequency division on the first LMFC of each data lane obtained by parsing comprises:

parsing received data of each data lane, and according to an Initial Lane Alignment (ILA) information already existing in the data of each data lane, parsing to obtain the first LMFC; and

according to the preset frequency division multiple, performing frequency division on the first LMFC obtained by parsing to obtain the second LMFC.

3. A non-transitory storage medium, comprising a set of instructions, which, when executed, causes at least one processor to execute the method according to claim 2.

4. The method according to claim 1, wherein, according to the second LMFC, writing the data of each data lane into the corresponding buffer comprises:

for each data lane, resetting a data write address of the corresponding buffer according to a first valid signal of the second LMFC, and then writing the data of each data lane into the corresponding buffer in sequence.

5. A non-transitory storage medium, comprising a set of instructions, which, when executed, causes at least one processor to execute the method according to claim 4.

6. The method according to claim 1, wherein, in each data lane, the data transmission delay difference is:

(N−

1)*T_LMFC;

where N is the preset frequency division multiple, and T_LMFC is the length of a standard LMFC.

7. A non-transitory storage medium, comprising a set of instructions, which, when executed, causes at least one processor to execute the method according to claim 6.

8. The method according to claim 1, wherein, according to the third LMFC, reading the data of each data lane from the corresponding buffer comprises:

for each data lane, resetting a read address of the corresponding buffer according to a first valid signal of the third LMFC, and then reading the data of each data lane from the corresponding buffer in sequence.

9. A non-transitory storage medium, comprising a set of instructions, which, when executed, causes at least one processor to execute the method according to claim 8.

10. A non-transitory storage medium, comprising a set of instructions, which, when executed, causes at least one processor to execute the method according to claim 1.

11. The method according to claim 1, wherein, according to the preset frequency division multiple, performing frequency division on the first LMFC of each data lane obtained by parsing comprises:

parsing received data of each data lane, and according to an Initial Lane Alignment (ILA) information already existing in the data of each data lane, parsing to obtain the first LMFC; and

according to the preset frequency division multiple, performing frequency division on the first LMFC obtained by parsing to obtain the second LMFC.

12. An apparatus for determining link delay, comprising a processor, a buffer and a memory for storing instructions executable by the processor;

wherein the processor is configured to implement;

a frequency division and write control unit, a read control unit, wherein

the frequency division and write control unit is configured to;

according to a preset frequency division multiple, perform frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and according to the second LMFC, write respectively data of each data lane into the corresponding buffer; and

the read control unit is configured to;

according to a SYSREF signal and a preset LMFC interval, generate a third LMFC, and according to the third LMFC, read respectively the data of each data lane from the corresponding buffer, wherein

a period of the second LMFC is the same as a period of the third LMFC;

wherein the period of the second LMFC corresponding to each data lane obtained after the frequency division is greater than a data transmission delay difference corresponding to a data lane having the maximum data transmission delay in all the data lanes before the frequency division.

13. The apparatus according to claim 12, wherein the processor is further configured to implement:

a frequency division module and a write module, wherein

the frequency division module is configured to;

according to the preset frequency division multiple, perform the frequency division on the first LMFC of each data lane obtained by parsing to obtain the second LMFC corresponding to each data lane; and

the write module is configured to;

according to the second LMFC generated by the frequency division module, write the data of each data lane into the corresponding buffer.

14. A communication device for determining link delay, comprising the apparatus according to claim 13.

15. The apparatus according to claim 12, wherein, the processor is further configured to implement:

an LMFC generation module and a read module, wherein

the LMFC generation module is configured to;

according to the SYSREF signal and the preset LMFC interval, generate the third LMFC;

the read module is configured to;

according to the third LMFC generated by the LMFC generation module, read respectively the data of each data lane from the corresponding buffer.

16. A communication device for determining link delay, comprising the apparatus according to claim 15.

17. A communication device for determining link delay, comprising the apparatus according to claim 12.