Fan-out semiconductor package
First Claim
1. A fan-out semiconductor package comprising:
- a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant covering the core member and the inactive surface of the semiconductor chip and filling at least portions of the through-hole;
a connection member including an insulating layer disposed on the first wiring layer of the core member and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and
a passivation layer disposed on the insulating layer and covering the redistribution layer,wherein (t2×
40%)<
t1<
(t2×
45%) which t1 is the thickness of the passivation layer and t2 is the distance from the inactive surface to the lower surface of the encapsulant.
2 Assignments
0 Petitions
Accused Products
Abstract
A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
13 Citations
21 Claims
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1. A fan-out semiconductor package comprising:
- a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering the core member and the inactive surface of the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer of the core member and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein (t2×
40%)<
t1<
(t2×
45%) which t1 is the thickness of the passivation layer and t2 is the distance from the inactive surface to the lower surface of the encapsulant. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
- a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;
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18. A fan-out semiconductor package comprising:
- a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering the core member and the inactive surface of the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer of the core member and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein (t2×
40%)<
t1<
(t2×
45%) in which t1 is the thickness of the passivation layer and t2 is the distance from the inactive surface to the lower surface of the encapsulant. - View Dependent Claims (19, 20, 21)
- a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;
Specification