Method and system for adapting solid state memory write parameters to satisfy performance goals based on degree of read errors

• US 10,403,366 B1
• Filed: 04/28/2017
• Issued: 09/03/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Inventors: Tabrizi, Haleh, Jeon, Seungjune, Cullen, Andrew
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US15/581,285
• Time in Patent Office: 858 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In general, embodiments of the technology relate to a method for adjusting solid state memory write parameters. The method includes obtaining a performance goal for the solid state memory, receiving a client write request for data from a client, where the client write request comprises a logical address and data to be written. The method further includes determining a physical address corresponding to the logical address, where the physical address comprises a page number for a physical page in the persistent storage, obtaining at least one verify threshold value using the performance goal, issuing a control module program request including the data to be written and the at least one verify threshold value to a storage module, where the storage module comprises the physical page, and programming the data into the physical page of the storage module using the at least one verify threshold value.

Claims

1. A method for adjusting solid state memory write parameters, the method comprising:

obtaining a performance goal for the solid state memory;

receiving a client write request for data from a client, wherein the client write request comprises a logical address and data to be written;

determining a physical address corresponding to the logical address, wherein the physical address comprises a page number for a physical page in the persistent storage;

obtaining at least one verify threshold value corresponding to at least one tuple comprising the performance goal and the page number;

issuing a control module program request comprising the data to be written and the at least one verify threshold value to a storage module, wherein the storage module comprises the physical page; and

programming the data into the physical page of the storage module using the at least one verify threshold value.

2. The method of claim 1, wherein the performance goal comprises extending the lifetime of the storage module.

3. The method of claim 2, further comprising, prior to receiving the client write request:

setting, based on the performance goal, the at least one verify threshold value to a level that results in occurrences of correctable read errors when data is read from the storage module, wherein, before being read, the data was written to the storage module using the at least one verify threshold value.

4. The method of claim 3, wherein the at least one verify threshold value is set below at least one default verify threshold value.

5. The method of claim 3, further comprising:

monitoring a read error rate; and

based on the read error rate, adjusting the at least one verify threshold value.

6. The method of claim 1, wherein the performance goal comprises enhancing read performance of the storage module.

7. The method of claim 6, further comprising, prior to receiving the client write request:

setting, based on the performance goal, the at least one verify threshold value to a level that reduces occurrences of correctable read errors when data is read from the storage module, wherein, before being read, the data was written to the storage module using the at least one verify threshold value.

8. The method of claim 6, further comprising:

detecting a correctable read error; and

based on the detection, adjusting the at least one verify threshold value.

9. The method of claim 1, further comprising:

determining a program/erase (P/E) cycle value associated with the physical page; and

wherein the at least one tuple further comprises the P/E cycle value.

10. The method of claim 9, wherein the P/E cycle value is a P/E cycle value range.

11. The method of claim 1, wherein the physical page is located on a solid-state module in the storage module, wherein the solid-state module comprises a multi-level cell (MLC).

12. The method of claim 11, wherein the at least one verify threshold value modifies at least one selected from a group consisting of an A threshold value, a B threshold value, and a C threshold value.

13. The method of claim 1, wherein obtaining the at least one verify threshold value comprises performing a look-up in an in-memory data structure, wherein the in-memory data structure comprises a plurality of entries, wherein each of the plurality of entries comprises at least one of a plurality of verify threshold values.

14. The method of claim 1, wherein the at least one verify threshold value comprises a voltage value.

15. The method of claim 1, wherein the at least one verify threshold value comprises a shift value, wherein the shift value corresponds to a voltage shift of a default verify threshold value.

16. A system, comprising:

a storage module comprising a storage module controller and solid state memory; and

a control module operatively connected to the storage module and a client,

wherein the control module;

obtains a performance goal for the solid state memory;

receives a client write request for data from a client, wherein the client write request comprises a logical address and data to be written;

determines a physical address corresponding to the logical address, wherein the physical address comprises a page number for a physical page in the persistent storage;

obtains at least one verify threshold value corresponding to at least one tuple comprising the performance goal and the page number; and

issues a control module program request comprising the data to be written and the at least one verify threshold value to a storage module, wherein the storage module comprises the physical page, and

wherein the storage module;

receives the control module program request; and

programs the data into the physical page of the storage module using the at least one verify threshold value.

17. The system of claim 16,

wherein the performance goal comprises extending the lifetime of the storage module;

and

wherein, based on the performance goal, the control module further, prior to receiving the client write request;

sets the at least one verify threshold value to a level that results in occurrences of correctable read errors when data is read from the storage module, wherein, before being read, the data was written to the storage module using the at least one verify threshold value.

18. The system of claim 16,

wherein the performance goal comprises enhancing read performance of the storage module;

and

wherein, based on the performance goal, the control module further, prior to receiving the client write request;

sets the at least one verify threshold value to a level that reduces occurrences of correctable read errors when data is read from the storage module, wherein, before being read, the data was written to the storage module using the at least one verify threshold value.

19. A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to:

obtain a performance goal for the solid state memory;

receive a client write request for data from a client, wherein the client write request comprises a logical address and data to be written;

determine a physical address corresponding to the logical address, wherein the physical address comprises a page number for a physical page in the persistent storage;

obtain at least one verify threshold value corresponding to at least one tuple comprising the performance goal and the page number;

issue a control module program request comprising the data to be written and the at least one verify threshold value to a storage module, wherein the storage module comprises the physical page; and

program the data into the physical page of the storage module using the at least one verify threshold value.