Semiconductor memory device and method of operating the same

• US 10,403,367 B2
• Filed: 07/17/2017
• Issued: 09/03/2019
• Est. Priority Date: 12/29/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Hye Lyoung, Lee, Bong Hoon, Lim, Chan
• Primary Examiner(s): Bashar, Mohammed A
• Application Number:
  US15/651,477
• Publication Number:
  US 20180190356A1
• Time in Patent Office: 778 Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.

Claims

1. A semiconductor memory device comprising:

a plurality of pages each comprising a plurality of memory cells;

peripheral circuits configured to perform a program operation on a selected page among the plurality of pages; and

a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page, and a compensation program voltage is applied to a word line coupled to the selected page to compensate threshold voltages of memory cells to be programmed to a highest program state after the main program operation is completed,

wherein the compensation program voltage is a positive voltage lower than a highest program voltage among program voltages used in the main program operation.

2. The semiconductor memory device according to claim 1, wherein the peripheral circuits comprise:

page buffers each including a plurality of latches configured to temporarily store data during the main program operation and apply the compensation program voltage, under control of the control logic; and

a voltage generation circuit configured to generate the program voltages increasing in steps during the main program operation and the compensation program voltage when the main program operation is completed, under the control of the control logic.

3. The semiconductor memory device according to claim 2, wherein the page buffers comprise:

first latches configured to store data inputted from an external device;

second latches configured to retain the data inputted from the external device when the main program operation is performed; and

third latches configured to temporarily store data to be used during the main program operation or apply the compensation program voltage.

4. The semiconductor memory device according to claim 3,

wherein the data stored in the third latches is changed depending on a result of a verify operation performed during the main program operation, and

wherein the data stored in the second latches is transmitted to the third latches when the main program operation is completed.

5. The semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuits such that the main program operation is performed in an incremental step pulse program (ISPP) manner, and when the main program operation is completed, the compensation program voltage is applied to the word line coupled to the selected page.

6. The semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuits such that the compensation program voltage is applied to the word line coupled to the selected page without a verify operation.

7. The semiconductor memory device according to claim 1,

wherein, when the main program operation of the selected page is completed, the control logic reloads data that is last used during the main program operation,

wherein the control logic adjusts voltages of bit lines coupled to the selected page depending on the loaded data, and

wherein the control logic controls the peripheral circuits such that the compensation program voltage is applied to the word line coupled to the selected page.

8. A method of operating a semiconductor memory device, comprising:

performing a main program operation on a selected page, wherein the main program operation includes a plurality of program loops comprising applying a program voltage to a word line coupled to the selected page and performing a verify operation of the selected page; and

performing a compensation program operation on memory cells programmed to a most significant program state among memory cells included in the selected page, when the verify operation passes and the main program operation is completed,

wherein the compensation program operation is performed by applying a compensation program voltage to the word line, and

wherein the compensation program voltage is a positive voltage lower than a highest program voltage which is used when the verify operation passes.

9. The method according to claim 8, wherein the main program operation is performed in an incremental step pulse program (ISPP) manner.

10. The method according to claim 9, wherein the main program operation is repeated while increasing a program voltage in steps until all pieces of logical data are programmed to the selected page.

11. The method according to claim 8, wherein the memory cells programmed to the most significant program state are set to memory cells programmed to a highest program state in the main program operation.

12. The method according to claim 11, wherein the memory cells that are programmed to the highest program state in the main program operation are selected depending on logical data that is last used in the main program operation.

13. A method of operating a semiconductor memory device, comprising:

inputting external data to first latches of page buffers;

transmitting the external data to second latches and third latches of the page buffers;

performing a main program operation and a verify operation on a selected page using data transmitted to the third latches;

retransmitting data stored in the second latches to the third latches if the verify operation has passed;

adjusting voltages of bit lines using the data retransmitted to the third latches; and

applying a compensation program voltage to a word line coupled to the selected page.

14. The method according to claim 13, further comprising, after the transmitting of the external data to the second latches and the third latches of the page buffers,

inputting external data to be programmed to a subsequent page to the first latches.

15. The method according to claim 13, wherein the data transmitted to the second latches is retained while the main program operation and the verify operation are performed.

16. The method according to claim 13, wherein the compensation program voltage is set to a positive voltage equal to or lower than a highest voltage of program voltages used in the main program operation.

17. The method according to claim 13, further comprising, after the applying of the compensation program voltage to the word line coupled to the selected page,

performing the inputting, the transmitting, the performing, the retransmitting, the adjusting, and the applying on a subsequent page.