Semiconductor memory device

• US 10,403,370 B2
• Filed: 01/02/2019
• Issued: 09/03/2019
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Tokiwa, Naoya
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US16/238,390
• Publication Number:
  US 20190139611A1
• Time in Patent Office: 244 Days
• Field of Search: 36518529, 36518522, 36518517
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Claims

1. A method for controlling a semiconductor memory device that comprises:

a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string,

the first memory string including

a first transistor,

a second transistor, and

a plurality of first memory cells,

the second memory string including

a third transistor,

a fourth transistor, and

a plurality of second memory cells;

a first bit line connected to a node of the first transistor and a node of the third transistor;

a first select gate line connected to a gate of the first transistor;

a second select gate line connected to a gate of the third transistor;

a source line connected to a node of the second transistor and a node of the fourth transistor; and

a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of the second memory cells, said method comprising;

performing an erase verify operation on the memory block, wherein the erase verify operation includes;

applying a first selection voltage to the first select gate line at a first time;

while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and

applying a second selection voltage to the second select gate line at a second time after the first time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time.

2. The method of claim 1, wherein the first selection voltage is substantially the same as the second selection voltage.

3. The method of claim 1, wherein the plurality of memory strings further includes a third memory string, the third memory string including a fifth transistor, a sixth transistor and a plurality of the third memory cells, a gate of the fifth transistor connected to a third select gate line, each one of the word lines further connected to one of gates of the third memory cells, and the erase verify operation further includes applying a third selection voltage to the third select gate line at a third time after the second time without making the voltage applied to the plurality of word lines zero voltage at any time between the second time and the third time.

4. The method of claim 1, wherein the semiconductor memory device further comprises:

a sense amplifier connected to the first bit line, wherein

during the erase verify operation, an enable signal for the sense amplifier is applied twice, once for the first memory string and once for the second memory string.

5. The method of claim 4, wherein during the erase verify operation, multiple loops of erase verify are carried out for each memory string.

6. A method for controlling a semiconductor memory device that comprises:

a plurality of memory strings including a first memory string and a second memory string, each of the memory strings including

a first transistor,

a second transistor, and

a plurality of memory cells serially connected between the first transistor and the second transistor,

a first bit line connected to nodes of the first transistors in the first memory string and the second memory string;

a first select gate line connected to a gate of the first transistor of the first memory string;

a second select gate line connected to a gate of the first transistor of the second memory string; and

a plurality of word lines connected to at least gates of memory cells of the first memory string and the second memory string, said method comprising;

performing an erase verify operation on the plurality of memory strings, wherein the erase verify operation includes;

applying a first selection voltage to the first select gate line at a first time;

while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and

applying a second selection voltage to the second select gate line at a second time after the first time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time.

7. The method of claim 6, wherein the first selection voltage is substantially the same as the second selection voltage.

8. The method of claim 6, wherein

the plurality of memory strings further includes a third memory string, a gate of the first transistor of the third memory string connected to a third select gate line, the plurality of word lines further connected to at least gates of the memory cells of the third memory string, and

the erase verify operation further includes applying a third selection voltage to the third select gate line at a third time after the second time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the third time.

9. The method of claim 6, wherein

the plurality of memory strings further includes a third memory string, a fourth memory string, a fifth memory string, a sixth memory string, a seventh memory string and an eighth memory string, a gate of the first transistor of the third memory string connected to a third select gate line, a gate of the first transistor of the fourth memory string connected to a fourth select gate line, a gate of the first transistor of the fifth memory string connected to a fifth select gate line, a gate of the first transistor of the sixth memory string connected to a sixth select gate line, a gate of the first transistor of the seventh memory string connected to a seventh select gate line, a gate of the first transistor of the eighth memory string connected to an eighth select gate line, and

the erase verify operation further includes the steps of applying a third selection voltage to the third select gate line at a third time after the second time, applying a fourth selection voltage to the fourth select gate line at a fourth time after the third time, applying a fifth selection voltage to the fifth select gate line at a fifth time after the fourth time, applying a sixth selection voltage to the sixth select gate line at a sixth time after the fifth time, applying a seventh selection voltage to the seventh select gate line at a seventh time after the sixth time, and applying an eighth selection voltage to the eighth select gate line at an eighth time after the seventh time, all of which steps are carried out without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the eighth time.

10. The method of claim 6, wherein the semiconductor memory device further comprises:

a sense amplifier connected to the first bit line, wherein

during the erase verify operation, an enable signal for the sense amplifier is applied at least twice, once for the first memory string and once the second memory string.

11. The method of claim 10, wherein during the erase verify operation, multiple loops of erase verify are carried out for each memory string.

12. A method for controlling a semiconductor memory device that comprises:

a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string,

the first memory string including

a first transistor,

a second transistor, and

a plurality of first memory cells,

the second memory string including

a third transistor,

a fourth transistor, and

a plurality of second memory cells;

a first bit line connected to a node of the first transistor and a node of the third transistor;

a first select gate line connected to a gate of the first transistor;

a second select gate line connected to a gate of the third transistor;

a source line connected to a node of the second transistor and a node of the fourth transistor; and

a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of the second memory cells, said method comprising;

performing an erase verify operation on the memory block, wherein the erase verify operation includes;

applying a first selection voltage to the first select gate line at a first time;

while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and

applying a second selection voltage to the second select gate line at a second time after the first time while keeping constant the voltage applied to the plurality of word lines between the first time and the second time.

13. The method of claim 12, wherein the first selection voltage is substantially the same as the second selection voltage.

14. The method of claim 12, wherein

the plurality of memory strings further includes a third memory string, the third memory string including a fifth transistor, a sixth transistor and a plurality of the third memory cells, a gate of the fifth transistor connected to a third select gate line, each one of the word lines further connected to one of gates of the third memory cells, and

the erase verify operation further includes applying a third selection voltage to the third select gate line at a third time after the second time while keeping constant the voltage applied to the plurality of word lines between the second time and the third time.

15. The method of claim 12, wherein the semiconductor memory device further comprises:

a sense amplifier connected to the first bit line, wherein

during the erase verify operation, an enable signal for the sense amplifier is applied twice, once for the first memory string and once for the second memory string.

16. The method of claim 15, wherein during the erase verify operation, multiple loops of erase verify are carried out for each memory string.

17. A method for controlling a semiconductor memory device that comprises:

a memory block including a plurality of memory strings, each of the memory strings being coupled to a different select gate line, the memory strings being coupled to a common bit line, the memory block being a unit of an erase verify operation, said method comprising

performing the erase verify operation on the memory block, wherein the erase verify operation includes;

selecting one of the memory strings at a first time;

while selecting the one of the memory strings, applying an erase verify voltage to the memory strings; and

selecting another one of the memory strings at a second time after the first time while keeping constant the voltage applied to the memory strings between the first time and the second time.

18. The method of claim 17, wherein the erase verify operation further includes:

selecting another one of the memory strings at a third time after the second time while keeping constant the voltage applied to the memory strings between the second time and the third time.

19. The method of claim 17, wherein the semiconductor memory device further comprises:

a sense amplifier connected to the first bit line, wherein

during the erase verify operation, an enable signal for the sense amplifier is applied twice, once for the memory string selected at the first time and once for the memory string selected at the second time.

20. The method of claim 19, wherein during the erase verify operation, multiple loops of erase verify are carried out for each memory string.