Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor

• US 10,403,384 B2
• Filed: 06/20/2017
• Issued: 09/03/2019
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/628,589
• Publication Number:
  US 20170372793A1
• Time in Patent Office: 805 Days
• Field of Search: 365201
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 : Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.

Claims

1. A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, including the steps of:

generating at least one assist signal in the normal mode of operation, the at least one assist signal including a read assist signal, wherein,

when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the at least one assist signal, and

inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated; and

generating a word line potential that is less than a first power supply potential in response to the read assist signal having the first assist logic level, wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the read operation wherein

the semiconductor device is powered by the first power supply potential.

6. The method of claim 1, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

2. A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, including the steps of:

generating at least one assist signal in the normal mode of operation, the at least one assist signal including a read assist signal, wherein,

when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the at least one assist signal, and

inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated; and

enabling a threshold voltage compensation circuit in response to the read assist signal having the first assist logic level, the threshold voltage compensation circuit is included in a sense amplifier circuit and compensates for differences in threshold voltages in a first insulated gate field effect transistor (IGFET) and a second IGFET during a read operation of data from the SRAM cell.

7. The method of claim 2, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by a first power supply potential, the SRAM circuit portion includes the SRAM cell.

3. A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, including the steps of:

generating at least one assist signal in the normal mode of operation, the at least one assist signal including a write assist signal, wherein,

when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the at least one assist signal, and

inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated; and

generating a write potential that is less than a reference potential in response to the write assist signal having the first assist logic level wherein a first power supply potential provides an upper power rail to the semiconductor device and the reference potential provides a lower power rail to the semiconductor device, a first bit line and a second bit line are connected to the SRAM cell and essentially the write potential is driven to one of the first or the second bit line during the write operation.

8. The method of claim 3, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

4. A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, including the steps of:

generating at least one assist signal in the normal mode of operation, the at least one assist signal including a write assist signal, wherein,

when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the at least one assist signal, and

inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated; and

generating a word line potential that is greater than a first power supply potential in response to the write assist signal having the first assist logic level wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the write operation and the semiconductor device is powered by the first power supply potential.

9. The method of claim 4, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

5. A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, including the steps of:

generating at least one assist signal in the normal mode of operation, the at least one assist signal including a write assist signal, wherein,

when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the at least one assist signal, and

inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated; and

generating a cell power supply potential that is less than a first power supply potential in response to the write assist signal having the first write assist logic level wherein the SRAM cell is coupled to receive and is powered by the cell power supply potential and the semiconductor device is powered by the first power supply potential.

10. The method of claim 5, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.