Manufacturing method of semiconductor device and semiconductor device

• US 10,403,513 B2
• Filed: 02/20/2018
• Issued: 09/03/2019
• Est. Priority Date: 03/21/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hashizume, Shoji, Takada, Keita
• Primary Examiner(s): Sayadian, Hrayr A
• Application Number:
  US15/900,416
• Publication Number:
  US 20180277397A1
• Time in Patent Office: 560 Days
• Field of Search: 257670
• CPC Class Codes: B29C 2045/0027 Gate or gate mark locations
• CPC Class Codes: B29C 45/0025 Preventing defects on the moulded article, e.g. weld lines, shrinkage marks preventing defects on the preformed parts or layers B29C45/14836
• CPC Class Codes: B29C 45/0046 Details relating to the filling pattern or flow paths or flow characteristics of moulding material in the mould cavity
• CPC Class Codes: B29C 45/14336 Coating a portion of the article, e.g. the edge of the article B29C45/14573 and B29C45/14598 take precedence
• CPC Class Codes: B29C 45/14655 connected to or mounted on a carrier, e.g. lead frame
• CPC Class Codes: B29L 2031/34 Electrical apparatus, e.g. sparking plugs or parts thereof
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H02P 27/06 : using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.

Claims

1. A semiconductor device comprising:

a first semiconductor chip;

a second semiconductor chip;

a first chip mounting portion on which the first semiconductor chip is mounted;

a second chip mounting portion on which the second semiconductor chip is mounted;

a plurality of first leads and a plurality of second leads each arranged on a corresponding periphery of the first chip mounting portion and the second chip mounting portion; and

an encapsulation body encapsulating the first semiconductor chip, the second semiconductor chip, the first chip mounting portion, the second chip mounting portion, a portion of each of the first leads, and a portion of each of the second leads,

wherein the encapsulation body includes a main surface and a back surface opposite to the main surface,

in plan view, the main surface includes;

a first side extending along a first direction;

a second side opposite to the first side;

a third side extending along a second direction orthogonal to the first direction; and

a fourth side opposite to the third side,

the encapsulation body further includes;

a first side surface attaching the first side to the back surface;

a second side surface attaching the second side to the back surface;

a third side surface attaching the third side to the back surface; and

a fourth side surface attaching the fourth side to the back surface,

the third side surface includes a resin injection trace,

in plan view, the plurality of first leads are arranged along the first side of the main surface,

in plan view, the plurality of second leads are arranged along the second side of the main surface,

the plurality of first leads each include an inner lead portion covered by the encapsulation body and an outer lead portion exposed to the outside of the encapsulation body,

the plurality of first leads include;

a third lead having the inner lead portion located between the first side and the first chip mounting portion in the second direction; and

a fourth lead having the inner lead portion not located between the first side and the first chip mounting portion,

in plan view, the first chip mounting portion includes;

a fifth side extending along the first side;

a sixth side opposite to the fifth side;

a seventh side extending along the third side; and

an eighth side opposite to the seventh side and extending along the fourth side,

in plan view, the fifth side of the first chip mounting portion is located between the first side and the sixth side of the first chip mounting portion,

a distance in the second direction from the fifth side of the first chip mounting portion to a first virtual line extending in the first direction and passing through a midpoint of the first side and the second side in the second direction is greater than a length of the inner lead portion of the third lead in the second direction,

a length of the inner lead portion of the fourth lead in the second direction is greater than the length of the inner lead portion of the third lead in the second direction,

the resin injection trace is located closer to the first side than to the second side in plan view,

a portion of the inner lead portion of the fourth lead is located between the first chip mounting portion and the resin injection trace in plan view,

in plan view, a spacing between the portion of the inner lead portion of the fourth lead and the resin injection trace in the first direction is smaller than a spacing between the portion of the inner lead portion of the fourth lead and the first chip mounting portion in the first direction, and

in plan view, the portion of the inner lead portion of the fourth lead is located on a second virtual line passing through the resin injection trace and extending along the first side.

2. The semiconductor device according to claim 1,

wherein a thickness of the resin injection trace in a third direction from the main surface to the back surface is less than a length from the third side to the fourth lead in the first direction.

3. The semiconductor device according to claim 1,

wherein the first semiconductor chip includes a plurality of first pad electrodes,

the second semiconductor chip includes a plurality of second pad electrodes,

the number of first pad electrodes is less than the number of second pad electrodes, and

a plane area of the first semiconductor chip is smaller than a plane area of the second semiconductor chip.

4. The semiconductor device according to claim 1,

wherein the length of the inner lead portion of the fourth lead in the second direction is greater than the distance from the first virtual line to the first side of the first chip mounting portion in the second direction.

5. The semiconductor device according to claim 1,

wherein the fourth lead is not electrically connected with either the first semiconductor chip or the second semiconductor chip.

6. The semiconductor device according to claim 1,

wherein the plurality of first leads include a fifth lead having the inner lead portion not located between the first side and the first chip mounting portion,

in plan view, the third lead is located between the fourth lead and the fifth lead, and

a length of the inner lead portion of the fifth lead in the second direction is less than the length of the inner lead portion of the fourth lead in the second direction.

7. The semiconductor device according to claim 1,

wherein the plurality of first leads include a sixth lead having the inner lead portion not located between the first side and the first chip mounting portion in the second direction,

in plan view, the sixth lead is located between the third lead and the fourth lead, and

the inner lead portion of the sixth lead and the inner lead portion of the fourth lead are connected to each other.