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Multilayer pillar for reduced stress interconnect and method of making same

  • US 10,403,590 B2
  • Filed: 02/28/2017
  • Issued: 09/03/2019
  • Est. Priority Date: 10/11/2007
  • Status: Active Grant
First Claim
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1. A method comprising:

  • forming a barrier and adhesion layer that connects a modulated copper pillar to a chip;

    forming a seed layer contacting the barrier and adhesion layer;

    forming a first copper layer contacting the seed layer;

    forming a second copper layer contacting a solder material;

    forming at least one deformation region, wherein the at least one-deformation region is between the first copper layer and the second copper layer and has a modulus of elasticity less than copper;

    forming a first protective layer interposed at an interface between a surface of the at least one deformation region and the first copper layer; and

    forming a second protective layer interposed at an interface between a surface of the second copper layer and the at least one deformation region and the second copper layer, wherein;

    the first protective layer is a layer of nickel covering the entire surface of the at least one deformation region; and

    the second protective layer is another layer of nickel covering the entire surface of the at least one deformation region.

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