System for reducing noise in a chemical sensor array

• US 10,404,249 B2
• Filed: 05/21/2018
• Issued: 09/03/2019
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Jordan, Jeremy, Rearick, Todd
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US15/984,947
• Publication Number:
  US 20180337671A1
• Time in Patent Office: 470 Days
• Field of Search: 327165, 327166, 327291-299, 327374, 327178, 326 93- 98, 716 6
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Claims

1. A system comprising:

a power supply;

a clock circuitry to generate a plurality of clock signals, each clock signal of the plurality of clock signals being synchronous with a primary clock signal, wherein each clock signal of the plurality of clock signals has a frequency, wherein a frequency of the primary clock signal is a respective multiple of the frequency of each of the clock signals of the plurality of clock signals, wherein each clock signal has a cycle that spans multiple cycles of the primary clock signal; and

a plurality of switchers, each switcher of the plurality of switchers communicatively coupled to the power supply, each switcher receiving a clock signal of the plurality of clock signals, wherein the clock circuitry is adapted to adjust one or more offsets of the plurality of clock signals to reduce a variance in a power draw from the power supply.

2. The system of claim 1, wherein the plurality of switchers is disposed on the same substrate.

3. The system of claim 1, further comprising a linear regulator coupled to one of the plurality of switchers.

4. The system of claim 1, wherein first, second, and third clock signals of the plurality of clock signals have different frequencies.

5. The system of claim 4, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal and the second frequency of the second clock signal is greater than a third frequency of the third clock signal, wherein the first frequency of the first clock signal is a multiple of the second frequency of the second clock signal and is a second multiple of the third frequency of the third clock signal.

6. The system of claim 5, wherein the second frequency of the second clock signal is a third multiple of the third frequency of the third clock signal.

7. The system of claim 5, wherein a rising edge of the first clock signal is offset by at least ½

cycle of the primary clock signal from a rising edge of the second clock signal.

8. The system of claim 5, wherein arising edge of the first clock signal is offset in a range of ½

to (n−

1)/2 cycles of the primary clock signal, where “

n”

is the number of cycles of the primary clock signal in a cycle of the second clock signal.

9. The system of claim 1, wherein at least two clock signals of the plurality of clock signals have the same frequency.

10. The system of claim 1, wherein rising edges of at least two clock signals of the plurality of clock signals are offset by at least ½

cycles of the primary clock signal.

11. The system of claim 1, wherein a first clock signal and a second clock signal of the plurality of clock signals have the same frequency, the second clock signal having a falling edge synchronous with a rising edge of the first clock signal.

12. A method of providing power to a circuitry, the method comprising:

supplying power with a power supply to a plurality of switchers;

generating a plurality of clock signals with a clock circuitry operably coupled to the plurality of switchers, each clock signal of the plurality of clock signals being synchronous with a primary clock signal, wherein each clock signal of the plurality of clock signals has a frequency, wherein a frequency of the primary clock signal is a respective multiple of the frequency of each of the clock signals of the plurality of clock signals, wherein each clock signal has a cycle that spans multiple cycles of the primary clock signal;

adjusting offsets of one or more of the plurality of clock signals to reduce a variance in a power draw from the power supply; and

supplying the plurality of clock signals to the plurality of switchers, each switcher receiving a clock signal of the plurality of clock signals.

13. The method of claim 12, wherein the plurality of switchers is disposed on the same substrate.

14. The method of claim 12, wherein first, second, and third clock signals of the plurality of clock signals have different frequencies.

15. The method of claim 14, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal and the second frequency of the second clock signal is greater than a third frequency of the third clock signal, wherein the first frequency of the first clock signal is a multiple of the second frequency of the second clock signal and is a second multiple of the third frequency of the third clock signal.

16. The method of claim 15, wherein a rising edge of the first clock signal is offset by at least ½

cycle of the primary clock signal from a rising edge of the second clock signal.

17. The method of claim 15, wherein a rising edge of the first clock signal is offset in a range of ½

to (n−

1)/2 cycles of the primary clock signal, where “

n”

is the number of cycles of the primary clock signal in a cycle of the second clock signal.

18. The method of claim 12, Wherein at least two clock signals of the plurality of clock signals have the same frequency.

19. The method of claim 12, wherein rising edges of at least two clock signals of the plurality of clock signals are offset by at least ½

cycles of the primary clock signal.

20. The method of claim 12, wherein a first clock signal and a second clock signal of the plurality of clock signals have the same frequency, the second clock signal having a falling edge synchronous with a rising edge of the first clock signal.