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Domain-differentiated power state coordination system

  • US 10,409,347 B2
  • Filed: 11/15/2018
  • Issued: 09/10/2019
  • Est. Priority Date: 12/22/2010
  • Status: Active Grant
First Claim
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1. A multi-core microprocessor with an inter-core operating state coordination system, the microprocessor comprising:

  • a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each having its own independently settable target operating state selected from a plurality of possible target operating states designating configurations for a plurality of resources;

    a plurality of resource-associated domains including first domains and second domains, wherein a first domain corresponds to a single core and first resources that are used only by the single core, wherein a plurality of first domains constitute a second domain, and the second domain corresponds to second resources that are used only by the cores of the plurality of first domains, wherein each first domain belongs to only one second domain and each second domain does not correspond to all cores and all resources; and

    coordination logic provided exclusively on each of the plurality of the cores, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, the coordination logic being configured to implement the core'"'"'s target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core.

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