Domain-differentiated power state coordination system

• US 10,409,347 B2
• Filed: 11/15/2018
• Issued: 09/10/2019
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: Lengjer Metal & Plastic Company Limited, VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Primary Examiner(s): Chan, Danny
• Application Number:
  US16/191,691
• Publication Number:
  US 20190107873A1
• Time in Patent Office: 299 Days
• Field of Search: None
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core'"'"'s target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

Claims

1. A multi-core microprocessor with an inter-core operating state coordination system, the microprocessor comprising:

a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each having its own independently settable target operating state selected from a plurality of possible target operating states designating configurations for a plurality of resources;

a plurality of resource-associated domains including first domains and second domains, wherein a first domain corresponds to a single core and first resources that are used only by the single core, wherein a plurality of first domains constitute a second domain, and the second domain corresponds to second resources that are used only by the cores of the plurality of first domains, wherein each first domain belongs to only one second domain and each second domain does not correspond to all cores and all resources; and

coordination logic provided exclusively on each of the plurality of the cores, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, the coordination logic being configured to implement the core'"'"'s target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core.

2. The multi-core microprocessor of claim 1, wherein for each resource-associated domain, a single core controls configuration of the resources specific to that domain, wherein each core that controls configuration of the second resources is a master core of the corresponding domain.

3. The multi-core microprocessor of claim 2, wherein the coordination logic for each core is configured to request one or more master cores to implement the target operating state to the extent that the one or more master cores are needed to implement the target operating state.

4. The multi-core microprocessor of claim 2, wherein each master core is configured to query other cores in the corresponding domain to determine whether an extent to which a target operating state from an originating core could be implemented for the domain without reducing performance of any of the non-originating cores below its own target operating state.

5. The multi-core microprocessor of claim 1, wherein when the core does not control configuration of a resource affected by the target operating state, and when the target operating state would re-enable or improve performance of that resource, the core'"'"'s coordination logic is configured to ask a master core that does control the resource to implement the target operating state affecting that resource.

6. The multi-core microprocessor of claim 1, further comprising sideband non-system-bus wires between the cores to pass operating state coordination messages between the cores.

7. The multi-core microprocessor of claim 1, wherein the coordination logic is configured to discover a most-achievable implementation of the target operating state, wherein the most-achievable implementation for a domain is an operating state closest to the target operating state that would not reduce performance of any of the other cores below its own target operating state.

8. The multi-core microprocessor of claim 7, the plurality of resource-associated domains further including a global domain, wherein all of the second domains constitute the global domain, and the global domain corresponds to global resources that are used by all of the cores.

9. The multi-core microprocessor of claim 8, wherein the coordination logic is configured to perform a domain-traversing operating state discovery process in which:

the logic discovers the most achievable implementation for the second domain of which the core is a part; and

when the most achievable operating state for the second domain would affect a global resource shared between second domains, the logic discovers the most achievable implementation for the global domain.

10. The multi-core microprocessor of claim 8, wherein the most-achievable implementation of the target operating state is equal to or between the target operating state and an existing operating state of the core.

11. A method of managing power consumption in a multi-core microprocessor, wherein a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each have an independently settable target operating state selected from a plurality of possible target operating states designating configurations for a plurality of resources;

wherein the cores are hierarchically organized into a plurality of resource-associated domains including first domains and second domains,

wherein a first domain corresponds to a single core and first resources that are used only by the single core, wherein a plurality of first domains constitute a second domain, and the second domain corresponds to second resources that are used only by the cores of the plurality of first domains, wherein each first domain belongs to only one second domain and each second domain does not correspond to all cores and all resources;

the method comprising;

an originating core receiving an instruction setting its target operating state; and

the originating core, in response to the instruction, executing coordination logic provided exclusively on the originating core, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination and configured to implement the target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core.

12. The method of claim 11, wherein for each resource-associated domain, a single core controls configuration of the resources specific to that domain, wherein each core that controls configuration of the second resources is a master core of the corresponding domain, the method further comprising:

requesting the master core to implement the target operating state to the extent that the one or more master cores are needed to implement the target operating state.

13. The method of claim 12, further comprising:

the master core querying other cores in the corresponding domain to determine an extent to which the originating core'"'"'s target operating state could be implemented for the domain without reducing performance of the other cores in the corresponding domain below their own target operating states.

14. The method of claim 11, further comprising:

when the core does not control configuration of a resource affected by the target operating state, and when the target operating state would re-enable or improve performance of that resource, asking a master core that does control the resource to implement the target operating state affecting that resource.

15. The method of claim 11, further comprising passing operating state coordination messages through sideband non-system-bus wires between the cores.

16. The method of claim 11, further comprising discovering a most-achievable implementation of the target operating state, wherein the most-achievable implementation for a domain is an operating state closest to the target operating state of the originating core that would not reduce performance of any of the non-originating cores below its own target operating state.

17. The method of claim 16, wherein the plurality of resource-associated domains further including a global domain, wherein all of the second domains constitute the global domain, and the global domain corresponds to global resources that are used by all of the cores.

18. The method of claim 17, further comprising:

discovering the most achievable implementation for the second domain of which the core is a part; and

when the most achievable operating state for the second domain would affect a global resource shared between second domains, discovering the most achievable implementation for the global domain.

19. The method of claim 17, wherein the most-achievable implementation of the target operating state is equal to or between the target operating state and an existing operating state of the core.

20. A method of managing power consumption in a multi-core microprocessor, the method comprising:

an operating system providing each of a plurality of cores, configured to coordinate with each other in a structured hierarchical manner, one of a plurality of independently settable target operating states, wherein each target operating state provides for a configuration of one or more first resources and one or more second resources, wherein a first resource is a resource used by only one core and a second resource is used by multiple cores, but not all cores;

each core implementing the configurations of the one or more first resources set forth in its own target operating state;

each core initiating a first discovery process to discover whether implementation of any configuration of any second resource in accordance with its own target operating state would reduce performance of any other core sharing the second resource hierarchically below the other core'"'"'s target operating state; and

each core executing coordination logic provided exclusively on the core, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, to implement any configuration of any second resource in accordance with its own target operating state only to the extent to which it would not reduce performance of any other core sharing the second resource below the other core'"'"'s target operating state.