Electronic device and data exchange method including protocol indicative of modes of operation

• US 10,409,735 B2
• Filed: 04/20/2016
• Issued: 09/10/2019
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chang, Kuen Long, Wang, Yu Chen, Chen, Ken Hui
• Primary Examiner(s): Park, Ilwoo
• Application Number:
  US15/133,864
• Publication Number:
  US 20170060785A1
• Time in Patent Office: 1,238 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

Claims

1. An electronic device, comprising:

a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus, the processor being configured to;

transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device;

transmit bits of data or memory address information; and

transmit a third bit indicative of a memory read mode or a memory write mode selected among;

reading data from the memory device at a serial peripheral interface speed,

reading data from the memory device at a speed faster than the serial peripheral interface speed,

erasing data block-by-block from the memory device, and

erasing all data from the memory device at once,

wherein

the third bit is transmitted after the bits of data or memory address information.

2. The electronic device according to claim 1, wherein the processor is further configured to transmit a fourth bit indicative of concluding communication with the memory device or retaining control of the data bus.

3. The electronic device according to claim 2, wherein the third bit is transmitted before the fourth bit.

4. The electronic device according to claim 1, wherein

the processor is further configured to receive at least two acknowledgements from the memory device, and

the third bit is transmitted after the at least two acknowledgements.

5. The electronic device according to claim 4, wherein:

the processor is further coupled to the memory device through a serial clock line;

the bits of data or memory address are eight bits long; and

the acknowledgements are transmitted every ninth signal of the serial clock line.

6. The electronic device according to claim 5, wherein the third bit is eight bits long.

7. The electronic device according to claim 1, wherein the processor is further configured to:

receive a first acknowledgement from the memory device between transmitting the message and transmitting the third bit; and

receive a second acknowledgement from the memory device between transmitting the bits of data or memory address information and transmitting the third bit.

8. The electronic device according to claim 7, wherein

the bits of data or memory address information are initial bits of data or memory address information;

and

the processor is further configured to;

receive a third acknowledgement from the memory; and

transmit subsequent bits of data or memory address information,

wherein the third acknowledgement is received between the third bit and the subsequent bits of data or memory address information.

9. The electronic device according to claim 1, wherein the processor and the memory device are compatible with an inter-integrated circuit protocol.

10. The electronic device according to claim 1, wherein to transmit bits of data or memory address, the processor is further configured to:

transmit a high byte of data or memory address;

receive an acknowledgement after transmitting the high byte; and

transmit a low byte of data or memory address after receiving the acknowledgement.

11. A memory device coupled to a control unit, through a data bus to receive and transmit bits on the data bus, the memory device being configured to:

receive a message from the control unit, the message including a first bit indicative of the control unit controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the control unit intends to read data from or write data to the memory device; and

receive bits of data or memory address information;

receive a third bit from the control unit, the third bit being indicative of a mode selected among;

reading data from the memory device at a serial peripheral interface speed,

reading data from the memory device at a speed faster than the serial peripheral interface speed,

erasing data block-by-block from the memory device, and

erasing all data from the memory device at once; and

wherein the third bit is received after the bits of data or memory address information.

12. The memory device according to claim 11, wherein the memory device is further configured to:

in response to the receipt of the message, transmit a first acknowledgement to the control unit; and

in response to the receipt of the third bit, transmit a second acknowledgement to the control unit.

13. The memory device according to claim 11, wherein the memory device is a flash memory device.

14. A data exchange method executable by an electronic device, the electronic device including a data bus, and a processor coupled to a memory device through the data bus to receive and transmit bits on the data bus, the method comprising:

transmitting, by the processor, a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device;

transmitting bits of data or memory address information, and

transmitting, by the processor, a third bit indicative of a memory read mode or a memory write mode selected among;

reading data from the memory device at a serial peripheral interface speed,

reading data from the memory device at a speed faster than the serial peripheral interface speed,

erasing data block-by-block from the memory device, and

erasing all data from the memory device at once,

wherein

the third bit is transmitted after the bits of data or memory address information.

15. The method according to claim 14, further comprising transmitting, by the processor, a fourth bit indicative of concluding communication with the memory device or retaining control of the data bus.

16. The method according to claim 15, wherein the third bit is transmitted before the fourth bit.

17. The method according to claim 14, further comprising:

receiving, by the processor, at least two acknowledgements from the memory device;

wherein the third bit is transmitted after receiving the at least two acknowledgements.

18. The method according to claim 14, further comprising:

receiving a first acknowledgement between transmitting the message and transmitting the third bit; and

receiving a second acknowledgement between transmitting the data or memory address information and transmitting the third bit.

19. The method according to claim 18, wherein

the bits of data or memory address information are initial bits of data or memory address information;

and

the method further comprises;

receiving, by the processor, a third acknowledgement; and

transmitting, by the processor, subsequent bits of data or memory address information,

wherein the third acknowledgement is received between the third bit and the subsequent bits of data or memory address information.

20. A data exchange method executable by a memory device coupled to a control unit through a data bus to receive and transmit bits on the data bus, the method comprising:

receiving a message from the control unit, the message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the control unit intends to read data from or write data to the memory device;

receiving bits of data or memory address information;

receiving a third bit from the control unit indicative of a memory read mode or a memory write mode of the memory device selected among;

reading data from the memory device at a serial peripheral interface speed,

reading data from the memory device at a speed faster than the serial peripheral interface speed,

erasing data block-by-block from the memory device, and

erasing all data from the memory device at once; and

wherein the third bit is received after the bits of data or memory address information.