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Interface for memory readout from a memory component in the event of fault

  • US 10,409,742 B2
  • Filed: 10/03/2016
  • Issued: 09/10/2019
  • Est. Priority Date: 10/07/2015
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) memory component comprising:

  • a memory core;

    a primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry, the primary interface for accessing the memory core during a normal mode of operation; and

    a secondary interface for accessing the memory core during a fault mode of operation, the fault mode of operation initiated in response to a detected fault in the IC memory component, wherein the fault is detected by an error code.

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