Interface for memory readout from a memory component in the event of fault

• US 10,409,742 B2
• Filed: 10/03/2016
• Issued: 09/10/2019
• Est. Priority Date: 10/07/2015
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Wright, Kenneth L.
• Primary Examiner(s): Duncan, Marc
• Application Number:
  US15/284,307
• Publication Number:
  US 20170103029A1
• Time in Patent Office: 1,072 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0784 Routing of error reports, e.g. with a specific transmission path or data flow
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Claims

1. An integrated circuit (IC) memory component comprising:

a memory core;

a primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry, the primary interface for accessing the memory core during a normal mode of operation; and

a secondary interface for accessing the memory core during a fault mode of operation, the fault mode of operation initiated in response to a detected fault in the IC memory component, wherein the fault is detected by an error code.

2. The IC memory component of claim 1, wherein:

during the fault mode of operation, the primary interface is disabled while the secondary interface is enabled.

3. The IC memory component of claim 1, wherein the primary interface is of a first data width, and wherein the secondary interface is of a second width that is less than the first data width.

4. The IC memory component of claim 3, wherein the secondary interface comprises a serial interface to transfer serialized signals.

5. The IC memory component of claim 1, wherein the IC memory component enters the fault mode of operation in response to the error code indicating a fault in the primary interface.

6. The IC memory component of claim 5, wherein the fault in the primary interface comprises a fault in the primary data I/O circuitry.

7. The IC memory component of claim 5, wherein the fault in the primary interface comprises a fault in the primary C/A input circuitry.

8. The IC memory component of claim 1, wherein during the fault mode, data stored in the memory core is accessed and transferred off-chip.

9. The IC memory component of claim 8, wherein the data is transferred to spare storage.

10. The IC memory component of claim 9, wherein the spare storage comprises a spare memory component.

11. The IC memory component of claim 1, wherein the secondary interface of the IC memory component is for coupling to a secondary interface of a second IC memory component via a serial bus.

12. A memory module comprising:

a primary databus connector;

multiple IC memory components coupled to the primary databus connector, each IC memory component including

a memory core,

a primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry, the primary interface for accessing the memory core during a normal mode of operation, and

a secondary interface for accessing the memory core during a fault mode of operation, the fault mode of operation initiated in response to a detected fault in the IC memory component, wherein the fault is detected by an error code;

a secondary data bus formed on the module; and

wherein the secondary interface from each of the multiple IC components is coupled to the secondary bus.

13. The memory module of claim 12, wherein the secondary interface from each of the multiple IC memory components is coupled to the secondary bus to form a daisy-chained configuration.

14. The memory module of claim 12, wherein at least one of the multiple IC memory components comprises a spare memory component to receive data from a memory component associated with the fault during the fault mode of operation.

15. The memory module of claim 12, wherein during the fault mode of operation, the secondary interface is enabled to carry out data transfer operations while the primary interface is disabled.

16. A memory system comprising:

a memory controller; and

a first memory module coupled to the memory controller via a primary databus, the first memory module including

a primary databus connector;

multiple IC memory components coupled to the primary databus connector, each IC memory component including

a memory core,

a primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry, the primary interface for accessing the memory core during a normal mode of operation, and

a secondary interface for accessing the memory core during a fault mode of operation, the fault mode of operation initiated in response to a detected fault in the IC memory component, wherein the fault is detected by an error code;

a secondary data bus formed on the module; and

wherein the secondary interface from each of the multiple IC components is coupled to the secondary bus.

17. The memory system of claim 16, wherein each of the multiple IC memory components further includes repair logic, and wherein the secondary interface is controlled by the repair logic.

18. The memory system of claim 16, wherein the secondary interface for each of the multiple IC memory components is controlled by the memory controller.

19. The memory system of claim 16, further comprising a second memory module coupled to the memory controller via the primary databus, and further comprising a lockstep mode of operation where the first and second memory modules operate in lockstep, and wherein data associated with the first and second memory modules is coded in accordance with the error code.