Semiconductor device and method for manufacturing the same

• US 10,411,003 B2
• Filed: 10/05/2017
• Issued: 09/10/2019
• Est. Priority Date: 10/14/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Okuno, Naoki, Nei, Kosei, Honda, Hiroaki, Yamade, Naoto, Fujiki, Hiroshi
• Primary Examiner(s): Reames, Matthew L
• Assistant Examiner(s): Bodnar, John
• Application Number:
  US15/725,519
• Publication Number:
  US 20180108647A1
• Time in Patent Office: 705 Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout

Abstract

A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide.

Claims

1. A semiconductor device comprising:

a first insulator over a substrate;

a first oxide semiconductor over the first insulator;

a second oxide semiconductor in contact with at least part of a top surface of the first oxide semiconductor;

a first conductor in contact with at least part of a top surface of the second oxide semiconductor;

a second conductor that is in contact with at least part of the top surface of the second oxide semiconductor and faces the first conductor;

a third oxide semiconductor that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide semiconductor;

a second insulator over the third oxide semiconductor;

a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and

a third insulator which is over the third conductor and at least part of which is in contact with a top surface of the first insulator,

wherein a side surface portion of the first oxide semiconductor, a side surface portion of the third oxide semiconductor, and a side surface portion of the second insulator are substantially aligned with one another,

wherein the first insulator comprises a first region that is in contact with the third insulator and a second region that is in contact with the first oxide semiconductor, and a thickness of the first region is less than a thickness of the second region, and

wherein the first oxide semiconductor comprises a first region that is in contact with the third oxide semiconductor and a second region that is in contact with the second oxide semiconductor, and a thickness of the first region of the first oxide semiconductor is less than a thickness of the second region of the first oxide semiconductor.

2. The semiconductor device according to claim 1,

wherein a side surface portion of the first conductor is substantially aligned with a side surface portion of the second oxide semiconductor,

wherein a side surface portion of the second conductor is substantially aligned with a side surface portion of the second oxide semiconductor, and

wherein the side surface portions of the second oxide semiconductor are located inward from side surface portions of the first oxide semiconductor.

3. The semiconductor device according to claim 2, wherein in a cross section in a channel width direction, a side surface portion of the third conductor is located inward from a side surface portion of the first oxide semiconductor.

4. The semiconductor device according to claim 1, wherein a difference between the thickness of the first region of the first insulator and the thickness of the second region of the first insulator is greater than or equal to 5 nm.

5. The semiconductor device according to claim 1, wherein in the first region of the first insulator, a spin density at a g-factor of approximately 2.0 in ESR measurement is lower than or equal to 2.0×

10¹⁷ spins/cm³.

6. The semiconductor device according to claim 1, further comprising:

a fourth conductor which is under the first insulator and at least part of which overlaps with the third conductor.

7. The semiconductor device according to claim 1,

wherein each of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor comprises indium, an element M, zinc, and oxygen, and

wherein the element M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf.

8. The semiconductor device according to claim 1, wherein the third insulator comprises oxygen and aluminum.

9. The semiconductor device according to claim 1, wherein an energy level of a conduction band minimum of each of the first oxide semiconductor and the third oxide semiconductor is closer to a vacuum level than an energy level of a conduction band minimum of the second oxide semiconductor is.

10. A semiconductor device comprising:

a first insulating film;

a first oxide semiconductor film over the first insulating film;

a second oxide semiconductor film over the first oxide semiconductor film;

a source electrode over the second oxide semiconductor film;

a drain electrode over the second oxide semiconductor film;

a second insulating film over the source electrode and the drain electrode;

a gate electrode over the second insulating film; and

a third insulating film over the gate electrode,

wherein the first insulating film comprises a first region that is in contact with the third insulating film and a second region that is in contact with the first oxide semiconductor film, and a thickness of the first region is less than a thickness of the second region, and

wherein a difference between the thickness of the first region and the thickness of the second region is greater than or equal to 10 nm.

11. The semiconductor device according to claim 10, wherein the third insulating film comprises aluminum oxide.