Semiconductor component having a doped substrate layer and corresponding methods of manufacturing

• US 10,411,097 B2
• Filed: 01/11/2018
• Issued: 09/10/2019
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Konrath, Jens Peter, Rupp, Roland, Hecht, Christian
• Primary Examiner(s): Junge, Bryan R
• Application Number:
  US15/868,619
• Publication Number:
  US 20180158916A1
• Time in Patent Office: 607 Days
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.

Claims

1. A semiconductor component, comprising:

a doped substrate layer cut from an initial wafer, the doped substrate layer forming a drain region, a rear-side contact zone, or an emitter of the semiconductor component;

a second layer grown directly on a first surface of the doped substrate layer, the second layer having a greater thickness than the doped substrate layer and a lesser doping density than the doped substrate layer; and

a metallic layer in direct contact with a second surface of the doped substrate layer opposite the first surface,

wherein the semiconductor component, the doped substrate layer and the second layer are each based on silicon carbide,

wherein the semiconductor component further comprises one or more trenches formed in the doped substrate layer,

wherein the doped substrate layer comprises p-type or n-type SiC,

wherein sidewalls of the one or more trenches are lined with SiC having an opposite doping type as the doped substrate layer,

wherein the one or more trenches is filled with a material of the second layer between the respective SiC lined sidewalls of the one or more trenches.

2. The semiconductor component of claim 1, wherein the thickness of the doped substrate layer is in a range of 5 μ

m to 20 μ

m and the thickness of the second layer is in a range of 20 μ

m to 200 μ

m.

3. The semiconductor component of claim 1, wherein the doping density of the doped substrate layer is in a range of 10¹⁸/cm³ to 10²⁰/cm³ and the doping density of the second layer is in a range of 10¹⁴/cm³ to 10¹⁷/cm³.

4. The semiconductor component of claim 1, wherein the doped substrate layer comprises a plurality of laterally oriented portions having alternate n-type and p-type doping.

5. The semiconductor component of claim 4, wherein the plurality of laterally oriented portions has nonuniform spacing and/or thickness.

6. The semiconductor component of claim 1, wherein the doped substrate layer comprises heavily doped p-type SiC, the second layer comprises lightly doped p-type SiC and the one or more trenches is filled with lightly doped p-type SiC between the respective SiC lined sidewalls of the one or more trenches, or wherein the doped substrate layer comprises heavily doped n-type SiC, the second layer comprises lightly doped n-type SiC and the one or more trenches is filled with lightly doped n-type SiC between the respective SiC lined sidewalls of the one or more trenches.

7. A method of manufacturing a semiconductor component, comprising:

forming a doped substrate layer in a semiconductor wafer, the doped substrate layer forming a drain region, a rear-side contact zone, or an emitter of the semiconductor component;

transferring the doped substrate layer of the semiconductor wafer to an acceptor wafer by an ion implantation process which comprises cutting the doped substrate layer from the semiconductor wafer and bonding the doped substrate layer to the acceptor wafer;

forming a component layer of the semiconductor component on a surface of the doped substrate layer facing away from the acceptor wafer, the component layer having a greater thickness than the doped substrate layer and a lesser doping density than the doped substrate layer;

detaching the acceptor wafer from the doped substrate layer after the component layer is formed; and

applying and annealing a metallization layer directly to a surface of the doped substrate layer that is exposed by detaching the acceptor wafer from the substrate layer,

wherein the semiconductor component and the doped substrate layer are both based on silicon carbide,

wherein the semiconductor component further comprises one or more trenches formed in the doped substrate layer,

wherein the method further comprises;

implanting sidewalls of the one or more trenches with a doping that is an opposite doping type as the doped substrate layer; and

filling the one or more trenches with a material of the component layer between the respective doped sidewalls of the one or more trenches.

8. The method of claim 7, further comprising forming an insulating layer on a surface of the doped substrate layer to which the acceptor wafer is to be attached prior to transferring the doped substrate layer to the acceptor wafer.

9. The method of claim 8, further comprising removing the insulating layer in addition to the acceptor wafer from the doped substrate layer and doping an exposed surface of the doped substrate layer.

10. The method of claim 7, further comprising forming a plurality of laterally oriented portions in the doped substrate layer and which have alternate n-type and p-type doping.

11. The method of claim 10, further comprising varying the spacing and/or thickness of the plurality of laterally oriented portions in the doped substrate layer.