Semiconductor device and method of manufacturing the semiconductor device

• US 10,411,139 B2
• Filed: 07/22/2017
• Issued: 09/10/2019
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yamashita, Tomohiro
• Primary Examiner(s): Fahmy, Wael M
• Assistant Examiner(s): Salerno, Sarah K
• Application Number:
  US15/657,136
• Publication Number:
  US 20180090626A1
• Time in Patent Office: 780 Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

protrusions that are each a portion of the semiconductor substrate, protrude from a top of the semiconductor substrate, and extend in a first direction along the top of the semiconductor substrate;

a first gate electrode that is provided over a top of each of the protrusions with a first insulating film in between, and extends in a second direction orthogonal to the first direction;

a second gate electrode that is provided over the top and a side face of the protrusions with a second insulating film including a charge storage part in between, is adjacent to one side face of the first gate electrode with the second insulating film in between, and extends in the second direction; and

a source region and a drain region that are provided in the protrusions so as to sandwich a channel region that is directly below a pattern including the first gate electrode and the second gate electrode,

wherein the first gate electrode, the second gate electrode, the source region, and the drain region configure a nonvolatile memory element,

wherein the second gate electrode includes a first semiconductor film formed on the second insulating film and a first metal film formed on the first semiconductor film, and the first semiconductor film and the first metal film are embedded between protrusions adjacent to each other in the second direction, and

wherein the first semiconductor film is interposed between the first metal film and the second insulating film.

2. The semiconductor device according to claim 1, wherein the second gate electrode includes the first semiconductor film, the first metal film, and a second semiconductor film formed in this order over the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the second semiconductor film is embedded between the protrusions adjacent to each other in the second direction.

4. The semiconductor device according to claim 2, wherein a top of the second semiconductor film is covered with a silicide layer.

5. The semiconductor device according to claim 2, wherein a top of the first metal film exists over a top of the second gate electrode, and a plug is coupled to the top of the first metal film.

6. The semiconductor device according to claim 2, wherein a bottom of a plug penetrating through the second semiconductor film is coupled to a top of the first metal film.

7. The semiconductor device according to claim 1,

wherein the second gate electrode includes the first semiconductor film, the first metal film, and a silicide layer formed in this order over the semiconductor substrate, and

wherein a bottom of the silicide layer is in contact with a top of the first metal film.

8. The semiconductor device according to claim 7, wherein the silicide layer is embedded between the protrusions adjacent to each other in the second direction.

9. The semiconductor device according to claim 1, wherein the second gate electrode includes the first semiconductor film, the first metal film, and a second metal film formed in this order over the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein the second metal film includes an aluminum film or a tungsten film.

11. The semiconductor device according to claim 1,

wherein the first semiconductor film includes a silicon film, and

wherein the first metal film includes a titanium nitride film.

12. The semiconductor device according to claim 1, wherein a silicon oxide film or an aluminum oxide film is interposed between the charge storage part and the second gate electrode.