Method of producing optoelectronic semiconductor chips

• US 10,411,155 B2
• Filed: 07/23/2015
• Issued: 09/10/2019
• Est. Priority Date: 07/31/2014
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Zini, Lorenzo, Frey, Alexander, Hertkorn, Joachim, Hahn, Berthold
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US15/327,697
• Publication Number:
  US 20170207363A1
• Time in Patent Office: 1,510 Days
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01S 5/0201 Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
• CPC Class Codes: H01S 5/0217 Removal of the substrate

Abstract

A method of producing optoelectronic semiconductor chips includes growing a semiconductor layer sequence on a growth substrate; applying at least one metallization to a contact side of the semiconductor layer sequence, which contact side faces away from the growth substrate; attaching an intermediate carrier to the semiconductor layer sequence, wherein a sacrificial layer is attached between the intermediate carrier and the semiconductor layer sequence; removing the growth substrate from the semiconductor layer sequence; structuring the semiconductor layer sequence into individual chip regions; at least partially dissolving the sacrificial layer; and subsequently removing the intermediate carrier, wherein, in removing the intermediate carrier, part of the sacrificial layer is still present, removing the intermediate carrier includes mechanically breaking remaining regions of the sacrificial layer, and the sacrificial layer is completely removed after removing the intermediate carrier.

Claims

1. A method of producing optoelectronic semiconductor chips comprising:

growing a semiconductor layer sequence on a growth substrate;

applying at least one metallization to a contact side of the semiconductor layer sequence, the contact side faces away from the growth substrate;

attaching an intermediate carrier to the semiconductor layer sequence, wherein a sacrificial layer is attached between the intermediate carrier and the semiconductor layer sequence and between at least two solder layers;

removing the growth substrate from the semiconductor layer sequence;

structuring the semiconductor layer sequence into individual chip regions;

at least partially dissolving the sacrificial layer by etching; and

subsequently removing the intermediate carrier such that remaining regions of the sacrificial layer are still present,

wherein,

removing the intermediate carrier comprises mechanically breaking the remaining regions of the sacrificial layer,

the sacrificial layer is completely removed after removing the intermediate carrier,

the intermediate carrier is fastened to the semiconductor layer sequence by at least one solder layer,

the sacrificial layer is in direct contact with the at least one solder layer, and

the sacrificial layer, immediately prior to removing the intermediate carrier, abuts, on two opposing main sides, directly to two of the at least two solder layers.

2. The method according to claim 1, wherein the chip regions are, in removing the intermediate carrier, fastened to a temporary carrier film and/or a die handler.

3. The method according to claim 1, wherein

the intermediate carrier is provided with one of the at least two solder layers,

the one of the at least two solder layers connects to the sacrificial layer,

the at least one metallization is composed of multiple metal layers and comprises a mirror layer made of aluminum or silver,

a thickness of the overall metallization is at least 70 nm and at most 500 nm,

the sacrificial layer is made of a metal oxide and has a thickness of at least 0.8 μ

m and at most 10 μ

m,

a thickness of the one of the at least two solder layers is at least 2 μ

m and at most 10 μ

m and is made of AuSn or NiSn,

the semiconductor layer sequence, the at least one metallization, the sacrificial layer and the one of the at least two solder layers are applied to an entire surface of the growth substrate and the intermediate carrier, and

after removing the growth substrate, the at least one metallization is also partitioned into the individual chip regions, and each of the chip regions is adapted for an optoelectronic semiconductor chip.

4. The method according to claim 1, wherein a plurality of elevations are either formed integrally with the intermediate carrier or the plurality of elevations are formed of a material different from the intermediate carrier and the sacrificial layer can selectively be etched with respect to the material.

5. The method according to claim 1, wherein electrical contact surfaces that externally electrically contact the completed semiconductor chip are provided on 1) a fastening side of the at least one metallization, the fastening side faces away from the semiconductor layer sequence, or provided on 2) a bottom side, facing away from the semiconductor layer sequence, of one of the at least two solder layers closest to the semiconductor layer sequence prior to removing the intermediate carrier.

6. The method according to claim 5, wherein the sacrificial layer is in some parts applied directly to the at least two solder layers forming the electrical contact surfaces or the at least one metallization, and

the electrical contact surfaces are covered by a cover material before attaching the sacrificial layer such that a material of the sacrificial layer does not directly touch the electrical contact surfaces.

7. The method according to claim 6, wherein the sacrificial layer is applied in a structured manner such that the sacrificial layer, viewed in projection onto the semiconductor layer sequence, only partially extends across the semiconductor layer sequence.

8. The method according to claim 7, wherein

the electrical contact surfaces are free of the sacrificial layer, and

a thickness of the sacrificial layer is at least 500 nm such that in the step of attaching the carrier substrate, solder is prevented from flowing out of the at least one solder layer located on a side of the sacrificial layer, the side of the sacrificial layer faces away from the semiconductor layer sequence, onto the electrical contact surfaces.

9. The method according to claim 5, wherein

the electrical contact surfaces are free of the sacrificial layer, and

a thickness of the sacrificial layer is at least 500 nm such that in the step of attaching the carrier substrate, solder is prevented from flowing out of the at least one solder layer located on a side of the sacrificial layer, which side of the sacrificial layer faces away from the semiconductor layer sequence, onto the electrical contact surfaces.

10. The method according to claim 1, wherein the sacrificial layer is partially directly applied to the at least two solder layers forming the electrical contact surfaces or the at least one metallization,

regions of the electrical contact surfaces remain free of the sacrificial layer, and

a thickness of the sacrificial layer is at least 500 run such that in the step of attaching the carrier substrate, solder is prevented from flowing out of the at least one solder layer located on a side of the sacrificial layer, the side of the sacrificial layer faces away from the semiconductor layer sequence, onto the electrical contact surfaces.

11. The method according to claim 1, wherein

the semiconductor layer sequence is based on AlInGaN,

the at least one metallization comprises Ag,

the intermediate carrier is provided with a solder layer,

the sacrificial layer is formed of ZnO,

the at least one solder layer comprises Sn and/or Au, and

at least one barrier layer made of a TiW alloy is located between the sacrificial layer and the at least one metallization.

12. A method of producing optoelectronic semiconductor chips comprising:

growing a semiconductor layer sequence on a growth substrate;

applying at least one metallization to a contact side of the semiconductor layer sequence, the contact side faces away from the growth substrate;

attaching an intermediate carrier to the semiconductor layer sequence, wherein a sacrificial layer is attached between the intermediate carrier and the semiconductor layer sequence;

removing the growth substrate from the semiconductor layer sequence;

structuring the semiconductor layer sequence into individual chip regions;

at least partially dissolving the sacrificial layer by etching; and

subsequently removing the intermediate carrier such that remaining regions of the sacrificial layer are still present,

wherein,

the removing of the intermediate carrier comprises mechanically breaking the remaining regions of the sacrificial layer,

the sacrificial layer is completely removed after the removing of the intermediate carrier,

the intermediate carrier is fastened to the semiconductor layer sequence by at least one solder layer,

the sacrificial layer is in direct contract with the at least one solder layer,

electrical contact surfaces that externally electrically contact the completed semiconductor chip are provided on

     1) a fastening side of the at least one metallization, the fastening side faces away from the semiconductor layer sequence, or provided on

     2) a bottom side, facing away from the semiconductor layer sequence, of one of at least two solder layers closest to the semiconductor layer sequence prior to removing the intermediate carrier,

regions of the electrical contact surfaces are free of the sacrificial layer, and

a thickness of the sacrificial layer is at least 500 nm such that in the step of attaching the carrier substrate, solder is prevented from flowing out of the solder layer located on a side of the sacrificial layer, the side of the sacrificial layer faces away from the semiconductor layer sequence, onto the electrical contact surfaces.

13. A method of producing optoelectronic semiconductor chips comprising:

growing a semiconductor layer sequence on a growth substrate;

applying at least one metallization to a contact side of the semiconductor layer sequence, the contact side faces away from the growth substrate;

attaching an intermediate carrier to the semiconductor layer sequence, wherein a sacrificial layer is attached between the intermediate carrier and the semiconductor layer sequence;

removing the growth substrate from the semiconductor layer sequence;

structuring the semiconductor layer sequence into individual chip regions;

at least partially dissolving the sacrificial layer by etching; and

subsequently removing the intermediate layer such that remaining regions of the sacrificial layer are still present,

wherein,

the removing of the intermediate carrier comprises mechanically breaking the remaining regions of the sacrificial layer,

the sacrificial layer is completely removed after the removing of the intermediate carrier,

the intermediate carrier is fastened to the semiconductor layer sequence by at least one solder layer,

the sacrificial layer is in direct contact with the at least one solder layer,

electrical contact surfaces that externally electrically contact the completed semiconductor chip are provided on

     1) a fastening side of the at least one metallization, the fastening side faces away from the semiconductor layer sequence, or provided on

     2) a bottom side, facing away from the semiconductor layer sequence, of one of at least two solder layers closest to the semiconductor layer sequence prior to removing the intermediate carrier,

the electrical contact surfaces are covered by a cover material before attaching the sacrificial layer such that a material of the sacrificial layer does not directly touch the electrical contact surfaces,

the sacrificial layer is applied in a structured manner such that the sacrificial layer, viewed in projection onto the semiconductor layer sequence, only partially extends across the semiconductor layer sequence,

the electrical contact surfaces are free of the sacrificial layer, and

a thickness of the sacrificial layer is at least 500 nm such that in the step of attaching the carrier substrate, solder is prevented from flowing out of the at least one solder layer located on a side of the sacrificial layer, the side of the sacrificial layer faces away from the semiconductor layer sequence, onto the electrical contact surfaces.