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Semiconductor light-emitting device including penetrating trenches

  • US 10,411,162 B2
  • Filed: 09/14/2016
  • Issued: 09/10/2019
  • Est. Priority Date: 08/27/2013
  • Status: Active Grant
First Claim
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1. A semiconductor light-emitting device, comprising:

  • a substrate;

    a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer formed on the substrate;

    a plurality of semiconductor constructions formed on the substrate, respectively comprising the first semiconductor layer, the second semiconductor layer, and the active layer;

    a plurality of first trenches penetrating the second semiconductor ;

    layer and the active layer to expose the first semiconductor layer;

    a second trench penetrating the second semiconductor layer and the active layer to expose a periphery region of the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the plurality of semiconductor constructions and the plurality of first trenches, wherein the first semiconductor layer of each of the plurality of semiconductor constructions are connected to each other through the first semiconductor layer exposed by the plurality of first trenches and the second trench in a cross-sectional view of the semiconductor light-emitting device, and the second semiconductor layer of each of the plurality of semiconductor constructions are separated from each other by one of the plurality of first trenches in a top view of the semiconductor light-emitting device;

    a patterned metal layer formed on the plurality of semiconductor constructions and filling in the plurality of first trenches and the second trench;

    a plurality of first pad portions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions; and

    a plurality of second pad portions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions,wherein the periphery region of first semiconductor layer comprises a top surface exposed by the second trench and a periphery side surface connecting to the top surface of the first semiconductor layer of the periphery region,wherein the periphery side surface is an exposed outermost side surface of the first semiconductor layer of the periphery region, andwherein the patterned metal layer comprises a plurality of first metal regions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions, and a second metal region electrically isolated to the plurality of first metal regions, and portions of the second metal region are formed in the plurality of first trenches and the second trench.

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