Data-driven phase detector element for phase locked loops

• US 10,411,922 B2
• Filed: 05/22/2017
• Issued: 09/10/2019
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Hormati, Ali
• Primary Examiner(s): Varndell, Ross
• Application Number:
  US15/602,080
• Publication Number:
  US 20180083809A1
• Time in Patent Office: 841 Days
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H04L 2203/02 differential
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

Claims

1. An apparatus comprising:

a data-driven phase comparator circuit configured to receive a plurality of data signals in parallel from a plurality of multi-input comparators (MICs) connected to a multi-wire bus, wherein at least one MIC is connected to at least three wires of the multi-wire bus, and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, each partial phase comparator configured to;

receive (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals;

responsive to a determination that a transition occurred in the corresponding data signal, generate a partial phase-error signal in analog form using a respective charge pump circuit of a plurality of charge pump circuits based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal;

a summation circuit configured to generate a composite phase-error signal based on at least two data signals of the plurality data signals by forming an analog summation of at least two partial phase-error signals received from corresponding partial phase comparators of the plurality of partial phase comparators; and

a loop filter connected to the summation circuit, the loop filter configured to receive the composite phase-error signal and to output a filtered phase-error signal.

2. The apparatus of claim 1, wherein each partial phase comparator further comprises a delay element, the delay element configured to introduce a sub-channel specific delay into the corresponding phase of the local oscillator signal.

3. The apparatus of claim 1, wherein each partial-phase comparator comprises a linear edge-triggered phase detector configured to form the comparison of the corresponding data signal and the corresponding phase of the local oscillator signal.

4. The apparatus of claim 1, wherein each partial-phase comparator comprises an edge-triggered bang-bang phase detector configured to form the comparison of the corresponding data signal and the corresponding phase of the local oscillator signal.

5. The apparatus of claim 1, wherein each partial phase comparator comprises a weighting circuit configured to apply a weight to the partial phase-error signal.

6. The apparatus of claim 1, wherein the plurality of data signals have a collective transition density above a predetermined threshold.

7. The apparatus of claim 1, wherein a partial phase comparator outputs a no-change result in response to determining no transition occurred.

8. The apparatus of claim 7, wherein the no-change result corresponds to the partial phase comparator being set in a high-impedance state.

9. A method comprising:

receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel from a plurality of multi-input comparators (MICs) connected to a multi-wire bus, wherein at least one MIC is connected to at least three wires of the multi-wire bus, and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators;

generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated as an analog signal formed using a respective charge pump circuit by;

receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals; and

responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal;

generating a composite phase-error signal based on at least two data signals of the plurality of data signals by forming an analog summation the plurality of partial phase error signals; and

filtering the composite phase-error signal.

10. The method of claim 9, further comprising introducing, for a given partial phase comparator, a sub-channel specific delay into the corresponding phase of the local oscillator signal, the sub-channel specific delay associated with the data signal received at the given partial phase comparator.

11. The method of claim 9, wherein the comparison of the corresponding phase of the local oscillator signal and the corresponding data signal is formed using a linear edge-triggered phase detector.

12. The method of claim 9, wherein the comparison of the corresponding phase of the local oscillator signal and the corresponding data signal is formed using an edge-triggered bang-bang phase detector.

13. The method of claim 9, further comprising applying a weight to the partial phase-error signal.

14. The method of claim 9, wherein the plurality of data signals have a collective transition density above a predetermined threshold.

15. The method of claim 9, wherein further comprising outputting a no-change result in response to determining no transition occurred.

16. The method of claim 15, wherein outputting the no-change result comprises setting the partial phase comparator in a high-impedance state.