Algorithm engine for ultra low-power processing of sensor data

• US 10,416,750 B2
• Filed: 09/26/2014
• Issued: 09/17/2019
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Black, Justin, Kulkarni, Rashmi, Sheynblat, Leonid
• Primary Examiner(s): Barbee, Manuel L
• Assistant Examiner(s): Nimox, Raymond L
• Application Number:
  US14/498,510
• Publication Number:
  US 20160091955A1
• Time in Patent Office: 1,817 Days
• Field of Search: None
• CPC Class Codes: G01D 9/005 Solid-state data loggers
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Disclosed is a method and apparatus for power-efficiently processing sensor data. In one embodiment, the operations implemented include: configuring a sensor fusion engine and a peripheral controller with a general purpose processor; placing the general purpose processor into a low-power sleep mode; reading data from a sensor and storing the data into a companion memory with the peripheral controller; processing the data in the companion memory with the sensor fusion engine; and awaking the general purpose processor from the low-power sleep mode.

Claims

1. A method for power-efficiently processing sensor data comprising:

configuring, by a general purpose processor, a sensor fusion engine that comprises a plurality of sensor data-processing algorithms implemented as hardware macros, each of the hardware macros comprising dedicated hardware circuitry for performing the corresponding sensor data-processing algorithm, wherein the plurality of sensor data-processing algorithms includes an algorithm, implemented as a hardware macro, for fusing of sensor data from multiple sensors;

upon the configuring, placing the general purpose processor into a low-power sleep mode;

in response to an interrupt from at least one of a plurality of sensors, waking a peripheral controller from a sleep mode;

after the waking, and with the peripheral controller, reading data produced by each of the plurality of sensors and storing the data into a companion memory while the general purpose processor is in the low-power sleep mode; and

processing the data stored into the companion memory with the sensor fusion engine,

wherein the configuring comprises configuring the sensor fusion engine to use the algorithm for fusing of sensor data from multiple sensors, implemented as a hardware macro, to perform the processing.

2. The method of claim 1, wherein the waking of the peripheral controller is performed by an Always-On Subsystem (AOSS), and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

3. The method of claim 1, wherein the sensor fusion engine, the companion memory, and the peripheral controller are located within a low power island of a System on a Chip (SoC) and

wherein a system clock of the SoC is turned off during the reading and processing.

4. The method of claim 1, wherein the sensor fusion engine is part of an Always-On Subsystem (AOSS) and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

5. The method of claim 1, wherein the algorithm for fusing combines data from disparate sensors to derive information.

6. A System on a Chip (SoC) comprising:

a companion memory;

a peripheral controller configured to read, from each of a plurality of sensors, data produced by the sensor and to store the data into the companion memory;

a subsystem configured to awaken the peripheral controller from a sleep mode in response to an interrupt from at least one of the plurality of sensors;

a sensor fusion engine configured to process the data stored into the companion memory; and

a general purpose processor configured to configure the sensor fusion engine before entering a low-power sleep mode,

wherein the sensor fusion engine comprises a plurality of sensor data-processing algorithms implemented as hardware macros, each of the hardware macros comprising dedicated hardware circuitry for performing the corresponding sensor data-processing algorithm, the plurality of sensor data-processing algorithms including an algorithm, implemented as a hardware macro, for fusing of sensor data from multiple sensors, and

wherein the sensor fusion engine is configurable by the general purpose processor to use the algorithm for fusing of sensor data from multiple sensors, implemented as a hardware macro, to process the data stored into the companion memory.

7. The System on a Chip (SoC) of claim 6, wherein the sensor fusion engine is configured to act as a math coprocessor to the general purpose processor.

8. The System on a Chip (SoC) of claim 6, wherein the waking of the peripheral controller is performed by an Always-On Subsystem (AOSS) and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

9. The System on a Chip (SoC) of claim 6, wherein the sensor fusion engine, the companion memory, and the peripheral controller are located within a low power island of the System on a Chip (SoC) that has a dedicated low power clock configured to be active when a system clock of the SoC is turned off.

10. The System on a Chip (SoC) of claim 6, wherein the sensor fusion engine is part of an Always-On Subsystem (AOSS), and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

11. The System on a Chip (SoC) of claim 6, wherein a particular configuration of the sensor fusion engine depends on an application of the general purpose processor requesting information derived from sensor data, and

wherein a particular configuration of the peripheral controller depends on the application requesting information derived from sensor data.

12. The System on a Chip (SoC) of claim 6, wherein the SoC further comprises a working memory that is separate from the companion memory and is configured to store instructions to be executed by the general purpose processor, and

wherein a storage capacity of the companion memory does not exceed several dozens of kilobytes.

13. The System on a Chip (SoC) of claim 6, wherein the algorithm for fusing combines data from disparate sensors to derive information.

14. A non-transitory computer-readable medium including:

code that, when executed by a peripheral controller, causes the peripheral controller to read, from each of a plurality of sensors, data produced by the sensor and to store the data into a companion memory;

code that, when executed by a subsystem, causes the subsystem to awaken the peripheral controller from a sleep mode in response to an interrupt from at least one of the plurality of sensors; and

code that, when executed by a general purpose processor, causes the general purpose processor to;

enter a low-power sleep mode; and

before entering the low-power sleep mode, configure a sensor fusion engine to process the data stored into the companion memory,

wherein the sensor fusion engine comprises a plurality of sensor data-processing algorithms implemented as hardware macros, each of the hardware macros comprising dedicated hardware circuitry for performing the corresponding sensor data-processing algorithm, the plurality of sensor data-processing algorithms including an algorithm, implemented as a hardware macro, for fusing of sensor data from multiple sensors, and

wherein the code that, when executed by the general purpose processor, causes the general purpose processor to configure the sensor fusion engine includes code that causes the general purpose processor to configure the sensor fusion engine to use the algorithm for fusing of sensor data from multiple sensors, implemented as a hardware macro, to process the data stored into the companion memory.

15. The non-transitory computer-readable medium of claim 14, wherein the subsystem is an Always-On Subsystem (AOSS) and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

16. An apparatus for power-efficiently processing sensor data comprising:

means for storing data;

means for controlling peripheral components, including means for reading, from each of a plurality of sensors, data produced by the sensor and storing the data read from each of the plurality of sensors into the means for storing;

means for waking, from a sleep mode, the means for controlling peripheral components in response to an interrupt from at least one of the plurality of sensors;

means for processing the data stored into the means for storing;

means for configuring the means for processing the data stored into the means for storing; and

means for placing the means for configuring into a low-power sleep mode upon the configuring,

wherein the means for processing the data stored into the means for storing comprises a plurality of sensor data-processing algorithms implemented as hardware macros, each of the hardware macros comprising dedicated hardware circuitry for performing the corresponding sensor data-processing algorithm, the plurality of sensor data-processing algorithms including an algorithm, implemented as a hardware macro, for fusing of sensor data from multiple sensors, and

wherein the means for processing the data stored into the means for storing is configurable by the means for configuring to use the algorithm for fusing of sensor data from multiple sensors, implemented as a hardware macro, to process the data stored into the means for storing.

17. The apparatus of claim 16, wherein the means for processing, the means for storing data, and the means for controlling peripheral components are located within a low power island of a System on a Chip (SoC) that has a dedicated low power clock configured to be active when a system clock of the SoC is turned off.

18. The apparatus of claim 16, wherein the means for waking is an Always-On Subsystem (AOSS) and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

19. The apparatus of claim 16, wherein the means for processing is part of an Always-On Subsystem (AOSS) and

wherein the AOSS is configured to configure a voltage rail of at least one among the general purpose processor, the sensor fusion engine, the companion memory, and the peripheral controller.

20. The apparatus of claim 16, wherein the algorithm for fusing combines data from disparate sensors to derive information.