Embedded computing device
First Claim
1. An apparatus comprising:
- at least one first processor core configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processor core;
at least one second processor core configured to run at least a second computer program application capable of further processing at least some information processed in said first processor core;
said first and second processor cores being interfaced with a shared information space, said shared information space consisting of an external memory space configured to serve as a logical memory unit with at least one address space mapped to both the first and the second processing unit,whereby a first application running in the first processor core is configured to enable said first processor core to write data retrieved from said processed signals to said information space, anda second application running in the second processor core is configured to receive a notification about said data being written to said shared information space, whereinsaid apparatus comprises at least one random access memory unit interfaced with the first and the second processing unit and which is configured to receive address data written by said first processing unit that is pointing to an address in said information space, and whereby said second processing unit is configured to read the written address in said at least one random access memory and to fetch data from said shared information space at said written address for further processing.
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Accused Products
Abstract
An apparatus and a method is provided that comprises at least one first processing unit configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processing unit, at least one second processing unit configured to run at least a second computer program application capable of further processing at least some information processed in said first processing unit. According to the invention the first and second processing unit are interfaced with a shared information space, whereby a first application running in the first processing unit is configured to enable said first processing unit to write data to said information space, and a second application running in the second processing unit is configured to receive a notification about said data being written to said shared information space, and to enable said second processing unit to retrieve from said information space said data written by said first processing unit for further processing.
25 Citations
27 Claims
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1. An apparatus comprising:
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at least one first processor core configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processor core; at least one second processor core configured to run at least a second computer program application capable of further processing at least some information processed in said first processor core; said first and second processor cores being interfaced with a shared information space, said shared information space consisting of an external memory space configured to serve as a logical memory unit with at least one address space mapped to both the first and the second processing unit, whereby a first application running in the first processor core is configured to enable said first processor core to write data retrieved from said processed signals to said information space, and a second application running in the second processor core is configured to receive a notification about said data being written to said shared information space, wherein said apparatus comprises at least one random access memory unit interfaced with the first and the second processing unit and which is configured to receive address data written by said first processing unit that is pointing to an address in said information space, and whereby said second processing unit is configured to read the written address in said at least one random access memory and to fetch data from said shared information space at said written address for further processing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method, comprising the steps of:
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receiving, by a first processor core, signals from at least one interface or device connected to said first processor core; processing said received signals in a first computer program application running on said first processor core; enabling said first computer program application to write data retrieved from said processed signals to a shared information space, the shared information space consisting of an external memory space interfaced with said first and second processing unit, and being configured to serve as a logical memory unit with at least one address space being interfaced with said first and second processing unit, enabling said first computer program application to write said address to at least one random access memory unit being interfaced with said first and second processing unit, reading in a second computer program application running in said second processing unit the address from said at least one random access memory, enabling said second computer program application to read said data stored in said shared information space at said address; and further processing said data in said second processor core. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. An apparatus comprising:
in a first processing unit comprising a first processor core, means for receiving and processing signals received from at least one interface or device connected to said first processing unit; means for enabling the first processor core to write data to a shared information space, said shared information space consisting of an external memory space configured to serve as a logical memory unit with at least one address space mapped to both the first processing unit and a second processing unit, means for notifying said second processing unit that data has been written to said shared information space, in said second processing unit comprising a second processor core, means to enable said second processor core to read from said shared information space data written by said first processor core; means to enable further processing of at least some information read from said shared information space being processed in said first processor core, and means for further processing of said read data in said second processor core to in order to display, communicate over a communication link, or to cause the second processing unit to enter a hibernation state.
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27. A computer program product being stored on a non-transitory computer readable medium, said computer program being configured to cause a method to be performed when run, the method comprising the steps of:
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receiving, by a first processor core, signals from at least one interface or device connected to said first processor core; processing said received signals in a first computer program application running on said first processor core; enabling said first computer program application to write data retrieved from said processed signals to a shared information space, said shared information space consisting of an external memory space configured to serve as a logical memory unit with at least one address space mapped to both the first and the second processing unit, receiving in a second computer program application running in a second processor core a notification of said data written to said shared information space, enabling said second computer program application to read said data stored in said shared information space; and further processing said data in said second processor core.
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Specification