Data driving system of liquid crystal display panel

• US 10,417,986 B2
• Filed: 07/21/2016
• Issued: 09/17/2019
• Est. Priority Date: 07/04/2016
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Xiong, Zhi
• Primary Examiner(s): Dharia, Prabodh M
• Application Number:
  US15/127,393
• Publication Number:
  US 20180218702A1
• Time in Patent Office: 1,153 Days
• Field of Search: 345 98, 345100, 345204-215, 4551271, 600300
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes

Abstract

A data driving system of a liquid crystal display panel includes a timing control chip; a plurality of data driving chips; a plurality of first signal lines, which is used to transmit a predetermined data signal from the timing control chip to the plurality of data driving chips, each first signal line being provided between the timing control chip and one of the plurality of data driving chips in order to transmit the predetermined data signal from the timing control chip to the plurality of data driving chips; and a plurality of first transmission gates, each of which is provided on one of the plurality of first signal lines. The data driving system can significantly improve the quality of the received signal of the data driving chip, and can effectively avoid the error of the received signal.

Claims

1. A data driving system of a liquid crystal display panel, comprising:

a timing control chip;

a plurality of data driving chips;

a plurality of first signal lines, which transmit a predetermined data signal from said timing control chip to said plurality of data driving chips, wherein each of said plurality of first signal lines is connected between said timing control chip and a respective one of said plurality of data driving chips in order to transmit said predetermined data signal from said timing control chip to said plurality of data driving chips;

a plurality of first transmission gates, wherein each of said plurality of first transmission gates is provided on a respective one of said plurality of first signal lines and is connected between the respective one of said plurality of first signal lines and a respective one of the plurality of data driving chips;

wherein said plurality of first transmission gates are connected, through said first signal lines, between said timing control chip and said plurality of data driving chips and said plurality of first transmission gates are controlled by said plurality of data driving chips to turn on and off, wherein said plurality of first transmission gates, when turned on, allow transmission of said predetermined data signal from said timing control chip, through said first signal lines, to said plurality of data driving chips.

2. The data driving system of a liquid crystal display panel as claimed in claim 1, wherein in a process of transmitting said predetermined data signal from said timing control chip to said plurality of data driving chips, said plurality of first transmission gates are not turned on simultaneously.

3. The data driving system of a liquid crystal display panel as claimed in claim 2, wherein in the process of transmitting said predetermined data signal from said timing control chip to said plurality of data driving chips, said plurality of first transmission gates are sequentially turned on, and when each first transmission gate is turned on, the other first transmission gates are turned off.

4. The data driving system of a liquid crystal display panel as claimed in claim 3, wherein one of said plurality of data driving chips is, in response to receiving a predetermined signal, controlling the first transmission gate on the first signal line connected thereto to be turned on, thereby receiving said predetermined data signal.

5. The data driving system of a liquid crystal display panel as claimed in claim 3, wherein one of said plurality of data driving chips that receives said predetermined data signal controls the first transmission gate on the first signal line connected thereto to be turned off after receiving said predetermined data signal, and transmits a control signal therefrom to one or more data driving chips of said plurality of data driving chips that do not receive said predetermined data signal, such that the one or more data driving chips of said plurality of data driving chips that receive the control signal controls the first transmission gate on the first signal line connected thereto to be turned on.

6. The data driving system of a liquid crystal display panel as claimed in claim 5, wherein said data driving system also comprises:

a plurality of second signal lines, which transmit a clock signal from said timing control chip to said plurality of data driving chips, wherein each of said plurality of second signal lines is connected between said timing control chip and a respective one of said plurality of data driving chips in order to transmit said clock signal to said plurality of data driving chips; and

a plurality of second transmission gates, wherein each of said plurality of second transmission gates is provided on a respective one of said plurality of second signal lines.

7. The data driving system of a liquid crystal display panel as claimed in claim 6, wherein the first transmission gate on the first signal line connected to one of said plurality of data driving chips and the second transmission gate on the second signal line connected to the one of said plurality of data driving chips are simultaneously turned on or off.

8. The data driving system of a liquid crystal display panel as claimed in claim 7, wherein each of said plurality of data driving chips, after receiving an Nth clock cycle of the clock signal, controls the first transmission gate on the first signal line connected thereto to be turned off, wherein N is an integer greater than 0.

9. The data driving system of a liquid crystal display panel as claimed in claim 2, wherein one of said plurality of data driving chips that receives said predetermined data signal controls the first transmission gate on the first signal line connected thereto to be turned off after receiving said predetermined data signal, and transmits a control signal therefrom to one or more data driving chips of said plurality of data driving chips that do not receive said predetermined data signal, such that the one or more data driving chips of said plurality of data driving chips that receive the control signal controls the first transmission gate on the first signal line connected thereto to be turned on.

10. The data driving system of a liquid crystal display panel as claimed in claim 9, wherein said data driving system also comprises:

a plurality of second signal lines, which transmit a clock signal from said timing control chip to said plurality of data driving chips, wherein each of said plurality of second signal lines is connected between said timing control chip and a respective one of said plurality of data driving chips in order to transmit said clock signal to said plurality of data driving chips; and

a plurality of second transmission gates, wherein each of said plurality of second transmission gates is provided on a respective one of said plurality of second signal lines.

11. The data driving system of a liquid crystal display panel as claimed in claim 10, wherein the first transmission gate on the first signal line connected to one of said plurality of data driving chips and the second transmission gate on the second signal line connected to the one of said plurality of data driving chips are simultaneously turned on or off.

12. The data driving system of a liquid crystal display panel as claimed in claim 11, wherein each of said plurality of data driving chips, after receiving an Nth clock cycle of the clock signal, controls the first transmission gate on the first signal line connected thereto to be turned off, wherein N is an integer greater than 0.

13. The data driving system of a liquid crystal display panel as claimed in claim 12, wherein one of said plurality of data driving chips that receives the clock signal, after receiving a Mth clock cycle of the clock signal, outputs the control signal to one or more data driving chips of said plurality of data driving chip that do not receive the clock signal, wherein M is a positive integer less than N, and

the one or more data driving chips of said plurality of data driving chips that receive the control signal control the second transmission gate on the second signal line connected thereto to delay (N-M) clock cycles to be turned on, so that when the one or more data driving chips of said plurality of data driving chips that receive the clock signal control the first transmission gate on the first signal line connected thereto to be turned off, the data driving chip that receives the control signal controls the first transmission gate on the first signal line connected thereto to be turned on.

14. The data driving system of a liquid crystal display panel as claimed in claim 1, wherein one of said plurality of data driving chips that receives said predetermined data signal controls the first transmission gate on the first signal line connected thereto to be turned off after receiving said predetermined data signal, and transmits a control signal therefrom to one or more data driving chips of said plurality of data driving chips that do not receive said predetermined data signal, such that the one or more data driving chips of said plurality of data driving chips that receive the control signal controls the first transmission gate on the first signal line connected thereto to be turned on.

15. The data driving system of a liquid crystal display panel as claimed in claim 14, wherein said data driving system also comprises:

a plurality of second signal lines, which transmit a clock signal from said timing control chip to said plurality of data driving chips, wherein each of said plurality of second signal lines is connected between said timing control chip and a respective one of said plurality of data driving chips in order to transmit said clock signal to said plurality of data driving chips; and

a plurality of second transmission gates, wherein each of said plurality of second transmission gates is provided on a respective one of said plurality of second signal lines.

16. The data driving system of a liquid crystal display panel as claimed in claim 15, wherein the first transmission gate on the first signal line connected to one of said plurality of data driving chips and the second transmission gate on the second signal line connected to the one of said plurality of data driving chips are simultaneously turned on or off.

17. The data driving system of a liquid crystal display panel as claimed in claim 16, wherein each of said plurality of data driving chips, after receiving an Nth clock cycle of the clock signal, controls the first transmission gate on the first signal line connected thereto to be turned off, wherein N is an integer greater than 0.

18. The data driving system of a liquid crystal display panel as claimed in claim 17, wherein one of said plurality of data driving chips that receives the clock signal, after receiving a Mth clock cycle of the clock signal, outputs the control signal to one or more data driving chips of said plurality of data driving chip that do not receive the clock signal, wherein M is a positive integer less than N, and

the one or more data driving chips of said plurality of data driving chips that receive the control signal control the second transmission gate on the second signal line connected thereto to delay (N-M) clock cycles to be turned on, so that when the one or more data driving chips of said plurality of data driving chips that receive the clock signal control the first transmission gate on the first signal line connected thereto to be turned off, the data driving chip that receives the control signal controls the first transmission gate on the first signal line connected thereto to be turned on.

19. The data driving system of a liquid crystal display panel as claimed in claim 18, wherein one of said plurality of data driving chips is, in response to receiving a predetermined signal, controlling the second transmission gate on the second signal line connected thereto to be turned on.

20. The data driving system of a liquid crystal display panel as claimed in claim 15, wherein said clock signal and said predetermined data signal are respectively transmitted in a differential signal mode.