Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory

• US 10,418,083 B2
• Filed: 08/08/2018
• Issued: 09/17/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Kawamura, Christopher J.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/058,202
• Publication Number:
  US 20180374528A1
• Time in Patent Office: 405 Days
• Field of Search: 365145, 365 63, 365 65, 365149
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region

Abstract

Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

Claims

1. An apparatus, comprising:

a capacitor having a first plate, a second plate, and a ferroelectric dielectric material;

a first digit line;

a first selection component configured to couple the first plate to the first digit line;

a second digit line; and

a second selection component configured to couple the second plate to the second digit line, wherein the first selection component is coupled to a first word line and is configured to be activated responsive to activation of the first word line and wherein the second selection component is coupled to a second word line and is configured to be activated responsive to activation of the second word line.

2. The apparatus of claim 1 wherein the first selection component is coupled between the first digit line and the first plate of the capacitor and wherein the second selection component is coupled between the second digit line and the second plate of the capacitor.

3. The apparatus of claim 1 wherein the first selection component, second selection component, and capacitor are vertically stacked.

4. An apparatus, comprising:

a ferroelectric memory cell including first and second selection components;

first and second digit lines coupled to the first and second selection components, respectively;

a first access line coupled to a gate of the first selection component;

a second access line coupled to a gate of the second selection component;

a sense component including a first sense node and a second sense node, the sense component configured to sense a voltage difference between the first and second sense nodes, amplify the voltage difference, and latch the voltage difference;

a first switch coupled to the first digit line and the first sense node, the first switch configured to selectively couple the first digit line to the first sense node;

a second switch coupled to the second digit line and the second sense node, the second switch coupled to selectively couple the second digit line to the second sense node, wherein the first switch is coupled to a first word line and is configured to be activated responsive to activation of the first word line and wherein the second switch is coupled to a second word line and is configured to be activated responsive to activation of the second word line.

5. The apparatus of claim 4, further comprising a driver circuit configured to provide a read voltage to the first digit line.

6. The apparatus of claim 4 wherein the sense component comprises:

a first p-type field effect transistor having a gate;

a first n-type field effect transistor having a gate coupled to the gate of the first p-type field effect transistor;

a second p-type field effect transistor having a gate; and

a second n-type field effect transistor having a gate coupled to the gate of the second p-type field effect transistor;

wherein the first sense node coupled to drains of the first p-type and first n-type field effect transistors, and further coupled to the gates of the second p-type and second n-type field effect transistors; and

wherein the second sense node coupled to drains of the second p-type and second n-type field effect transistors, and further coupled to the gates of the first p-type and first n-type field effect transistors.

7. The apparatus of claim 6, further comprising:

a plurality of first access lines each coupled to the first selection component of each respective ferroelectric memory cell of a plurality of ferroelectric memory cells, the plurality of ferroelectric memory cells including the ferroelectric memory cell; and

a plurality of second access lines each coupled to the second selection component of each respective ferroelectric memory cell of the plurality of ferroelectric memory cells.

8. The apparatus of claim 4 wherein the ferroelectric memory cell comprises:

a first plate coupled to the first selection component;

a second plate coupled to the second selection component; and

a ferroelectric material positioned between the first and second plates.

9. The apparatus of claim 4, further comprising a reference switch coupled to the first sense node and configured to provide a reference voltage to the first sense node.

10. The apparatus of claim 4, further comprising:

a plurality of ferroelectric memory cells coupled to the first and second digit lines, each of the ferroelectric memory cells of the plurality of ferroelectric memory cells including respective first and second selection components.

11. The apparatus of claim 4 wherein the first and second digit lines are vertically offset relative to one another, and a ferroelectric capacitor vertically between the first and second selection components.

12. An apparatus comprising:

a plurality of memory cells arranged in rows and columns, each memory cell including first and second selection components, and further including a ferroelectric capacitor coupled between the first and second selection components;

a plurality of pairs of word lines, each pair of word lines of the plurality of pairs of word lines coupled to a respective row of memory cells;

a plurality of pairs of digit lines, each pair of digit lines of the plurality of pairs of digit lines coupled to a respective column of memory cells, wherein each of the plurality of pairs of digit lines includes a first digit line coupled to the first selection components of the memory cells of the respective column of memory cells and further includes a second digit line coupled to the second selection components of the memory cells of the respective column of memory cells;

a row decoder coupled to the plurality of pairs of word lines and configured to activate a pair of word lines based on a row address;

a column decoder coupled to the plurality of pairs of digit lines and configured to activate a pair of digit lines based on a column address; and

sense components coupled to the plurality of pairs of digit lines and configured to determine the stored states of the memory cells of an activated row of memory cells, wherein the sense components comprises a respective sense component coupled to each of the pairs of digit lines of the plurality of pairs of digit lines, wherein each sense component is configured to drive the second digit line of the pair of digit lines to which the sense component is coupled to a voltage and the sense component is further configured to drive the first digit line of the pair of digit lines to which the sense component is coupled to a voltage complementary to the voltage of the second digit line, wherein each memory cell of the plurality of memory cells restores a data state responsive to a respective sense component driving the first digit line to the voltage complementary to the voltage of the second digit line.

13. The apparatus of claim 12 wherein each pair of word lines of the plurality includes a first word line coupled to gates of the first selection components of the respective row of memory cells and further includes a second word line coupled to gates of the second selection components of the respective row of memory cells, wherein the first selection components of the respective row of memory cells are activated by the first word line and the second selection components of the respective row of memory cells are activated by the second word line.

14. The apparatus of claim 12 wherein the first selection component, second selection component, and ferroelectric capacitor are vertically stacked and the ferroelectric capacitor is vertically between the first and second selection components.

15. The apparatus of claim 12, wherein each memory cell of the plurality of memory cells comprises an initial data state, and wherein each sense component is configured to drive a digit line of a respective pair of the plurality of pairs of digit lines to a complementary voltage to a voltage of the other digit line of the respective pair of the plurality of pairs of digit lines.

16. The apparatus of claim 15, wherein each memory cell of the plurality of memory cells restores the initial data state responsive to a respective sense component driving the digit line of the respective pair to the voltage complementary to the voltage of the other digit line of the respective pair.