Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

• US 10,418,303 B2
• Filed: 08/21/2018
• Issued: 09/17/2019
• Est. Priority Date: 12/21/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsley, Thomas H.
• Primary Examiner(s): Henry, Caleb E
• Application Number:
  US16/106,241
• Publication Number:
  US 20180374774A1
• Time in Patent Office: 392 Days
• Field of Search: 257713
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

Claims

1. A semiconductor die assembly, comprising:

a first semiconductor die having a first major surface and an opposite second major surface;

a package substrate underlying the first semiconductor die when the semiconductor die assembly is in a given orientation;

an interposer between the package substrate and the first semiconductor die, wherein the interposer has a first major surface and an opposite second major surface, and wherein the first semiconductor die is electrically coupled to the interposer via the first major surface of the interposer;

a second semiconductor die having a first major surface and an opposite second major surface, wherein the package substrate is electrically coupled to the second semiconductor die via the second major surface of the second semiconductor die, and wherein the first major surface of the second semiconductor die is below the first major surface of the interposer when the semiconductor die assembly is in the given orientation; and

a heat spreader configured to transfer heat away from the first and second semiconductor dies, wherein the heat spreader includes—

a cap thermally coupled to the first semiconductor die via the first major surface of the first semiconductor die, and

a pillar thermally coupled to the second semiconductor die via the first major surface of the second semiconductor die, wherein the interposer extends around at least a majority of a perimeter of the pillar in a plane parallel to the first major surface of the interposer.

2. The semiconductor die assembly of claim 1 wherein:

the interposer defines an opening; and

the pillar extends through the opening.

3. The semiconductor die assembly of claim 1 wherein the interposer is shaped as a rectangular annulus.

4. The semiconductor die assembly of claim 1 wherein:

the first semiconductor die is a memory die; and

the second semiconductor die is a logic die.

5. The semiconductor die assembly of claim 1 wherein:

the heat spreader includes fins configured to transfer heat by convection; and

the fins are above the pillar when the semiconductor die assembly is in the given orientation.

6. The semiconductor die assembly of claim 1 wherein the cap and the pillar are contiguous components of the heat spreader.

7. The semiconductor die assembly of claim 1 wherein:

the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;

the first one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a first direction;

the semiconductor die assembly further comprises a second one of the plurality of first semiconductor dies; and

the second one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a second direction opposite to the first direction.

8. The semiconductor die assembly of claim 1 further comprising:

a first thermal interface feature through which the cap is thermally coupled to the first semiconductor die; and

a second thermal interface feature through which the pillar is thermally coupled to the second semiconductor die, wherein the second thermal interface feature is below the first major surface of the interposer when the semiconductor die assembly is in the given orientation.

9. The semiconductor die assembly of claim 8 wherein the first and second thermal interface features are, respectively, first and second pieces of thermal interface tape.

10. The semiconductor die assembly of claim 8 wherein the first and second thermal interface features are, respectively, first and second volumes of thermal interface paste.

11. The semiconductor die assembly of claim 1 wherein:

the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;

the semiconductor die assembly further comprises a second one of the plurality of first semiconductor dies; and

the second one of the plurality of first semiconductor dies is electrically coupled to the interposer via the second major surface of the interposer.

12. The semiconductor die assembly of claim 11, further comprising heat transfer material between the package substrate and the second one of the plurality of first semiconductor dies, wherein the heat transfer material is thermally coupled to the second one of the plurality of first semiconductor dies.

13. The semiconductor die assembly of claim 12 wherein the heat transfer material is a metal film overlying the package substrate when the semiconductor die assembly is in the given orientation.

14. The semiconductor die assembly of claim 12 further comprising a thermal interface feature through which the heat transfer material is thermally coupled to the second one of the plurality of first semiconductor dies.

15. The semiconductor die assembly of claim 14 wherein the thermal interface feature is a piece of thermal interface tape.

16. The semiconductor die assembly of claim 14 wherein the thermal interface feature is a volume of thermal interface paste.

17. A method for making a semiconductor die assembly, the method comprising:

electrically coupling a first semiconductor die to an interposer via a major surface of the interposer;

electrically coupling a second semiconductor die to a package substrate;

thermally coupling a cap of a heat spreader to the first semiconductor die, wherein the heat spreader is configured to transfer heat away from the first semiconductor die via the cap;

locating a pillar of the heat spreader relative to the interposer such that the interposer extends around at least 75% of a perimeter of the pillar, wherein the heat spreader is configured to transfer heat away from the second semiconductor die via the pillar; and

thermally coupling the pillar of the heat spreader to the second semiconductor die via a major surface of the second semiconductor die, wherein the major surface of the second semiconductor die is inset toward the package substrate relative to the major surface of the interposer.

18. The method of claim 17 wherein:

the interposer defines an opening; and

locating the pillar relative to the interposer includes extending the pillar through the opening.

19. A semiconductor die assembly, comprising:

a first semiconductor die having a first major surface and an opposite second major surface;

a package substrate underlying the first semiconductor die when the semiconductor die assembly is in a given orientation;

a single interposer between the package substrate and the first semiconductor die, wherein the interposer has a first major surface, an opposite second major surface, and an opening extending from the first major surface to the second major surface, and wherein the first semiconductor die is electrically coupled to the interposer via the first major surface of the interposer;

a second semiconductor die having a first major surface and an opposite second major surface, wherein the package substrate is electrically coupled to the second semiconductor die via the second major surface of the second semiconductor die, and wherein the first major surface of the second semiconductor die is below the first major surface of the interposer when the semiconductor die assembly is in the given orientation; and

a heat spreader configured to transfer heat away from the first and second semiconductor dies, wherein the heat spreader includes—

a cap thermally coupled to the first semiconductor die via the first major surface of the first semiconductor die, and

a pillar thermally coupled to the second semiconductor die via the first major surface of the second semiconductor die, wherein the pillar extending through the opening of the interposer.