Semiconductor device

• US 10,418,321 B2
• Filed: 04/16/2018
• Issued: 09/17/2019
• Est. Priority Date: 06/20/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kuwabara, Shinichi, Iida, Tetsuya, Nakashiba, Yasutaka
• Primary Examiner(s): Potter, Roy K
• Application Number:
  US15/954,213
• Publication Number:
  US 20180366409A1
• Time in Patent Office: 519 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 Optical coupling
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

Claims

1. A semiconductor device comprising:

a first semiconductor chip;

a second semiconductor chip located opposite to the first semiconductor chip;

a first insulating film interposed between the first semiconductor chip and the second semiconductor chip facing each other; and

a sealing body sealing the first semiconductor chip, the second semiconductor chip, and the first insulating film,

the first semiconductor chip comprising;

a first semiconductor substrate having a first surface and

a second surface opposite to the first surface;

a first multilayer wiring layer provided between the first surface of the first semiconductor substrate and the first insulating film, the first multilayer wiring layer including a first wiring for a first integrated circuit; and

a first coil provided in the first multilayer wiring layer,

the second semiconductor chip comprising;

a second semiconductor substrate having a third surface facing the first surface of the first semiconductor chip and a fourth surface opposite to the third surface;

a second multilayer wiring layer provided between the third surface of the second semiconductor substrate and the first insulating film, the second multilayer wiring layer including a second wiring for a second integrated circuit;

a second coil provided in the second multilayer wiring layer, facing the first coil through the first insulating film, and magnetically coupled to the first coil; and

the second wiring for the second integrated circuit formed just above the second coil,

wherein the first coil is located in a manner to overlap part of a first circuit region located in the first surface of the first semiconductor substrate in plan view,

wherein the second coil is located in a manner to overlap part of a second circuit region located in the third surface of the second semiconductor substrate in plan view,

wherein the first wiring is located just under the first coil, and

wherein the second wiring is located just above the second coil.

2. The semiconductor device according to claim 1, wherein an operating frequency of the first coil and the second coil during operation is 200 MHz or less.

3. The semiconductor device according to claim 1,

wherein in the first multilayer wiring layer, a first shield pattern is provided in a wiring layer one level lower than the first coil in a manner to overlap the first coil in plan view, and

wherein in the second multilayer wiring layer, a second shield pattern is provided in a wiring layer one level lower than the second coil in a manner to overlap the second coil in plan view.

4. The semiconductor device according to claim 3, wherein the first shield pattern and the second shield pattern are electrically coupled to a reference potential.

5. The semiconductor device according to claim 3, wherein the first shield pattern and the second shield pattern are larger than a diameter of the first coil and the second coil in plan view.

6. The semiconductor device according to claim 1,

wherein in the first multilayer wiring layer, a first wiring prohibition area is provided in a wiring layer one level lower than the first coil in a manner to overlap the first coil in plan view, and

wherein in the second multilayer wiring layer, a second wiring prohibition area is provided in a wiring layer one level lower than the second coil in a manner to overlap the second coil in plan view.

7. The semiconductor device according to claim 6, wherein the first wiring prohibition area and the second wiring prohibition area are larger than a diameter of the first coil and the second coil in plan view.

8. The semiconductor device according to claim 1, wherein a digital circuit is provided in the part of each of the first circuit region and the second circuit region.

9. A semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface opposite to the first surface;

a multilayer wiring layer provided over the first surface of the semiconductor substrate, the multi multilayer wiring including a first wiring for an integrated circuit;

a first coil provided in the multilayer wiring layer;

a second coil provided in the multilayer wiring layer, facing the first coil, and magnetically coupled to the first coil; and

a second insulating film interposed between the first coil and the second coil,

wherein the first coil is located in a wiring layer lower than the second coil,

wherein the first coil and the second coil are arranged in a manner to overlap part of a circuit region provided in the first surface of the semiconductor substrate in plan view, and

wherein the first wiring is located just under the first coil.

10. The semiconductor device according to claim 9, wherein an operating frequency of the first coil and the second coil during operation is 200 MHz or less.

11. The semiconductor device according to claim 9, wherein in the multilayer wiring layer, a shield pattern is provided in a wiring layer one level lower than the first coil in a manner to overlap the first coil in plan view.

12. The semiconductor device according to claim 11, wherein the shield pattern is electrically coupled to a reference potential.

13. The semiconductor device according to claim 11, wherein the shield pattern is larger than a diameter of the first coil and the second coil in plan view.

14. The semiconductor device according to claim 9, wherein in the multilayer wiring layer, a wiring prohibition area is provided in a wiring layer one level lower than the first coil in a manner to overlap the first coil in plan view.

15. The semiconductor device according to claim 14, wherein the wiring prohibition area is larger than a diameter of the first coil and the second coil in plan view.

16. The semiconductor device according to claim 9, wherein a digital circuit is provided in the part of the circuit region.