Multi-level semiconductor memory device and structure

• US 10,418,369 B2
• Filed: 05/26/2018
• Issued: 09/17/2019
• Est. Priority Date: 10/24/2015
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Han, Jin-Woo
• Primary Examiner(s): Fourson, III, George R
• Application Number:
  US15/990,611
• Publication Number:
  US 20180350823A1
• Time in Patent Office: 479 Days
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 : characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.

Claims

1. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first memory cells and a first control line;

a second level comprising a second array of second memory cells and a second control line;

a third level comprising a third array of third memory cells and a third control line,

wherein said second level overlays said first level, and

wherein said third level overlays said second level;

a first access pillar;

a second access pillar;

a third access pillar; and

memory control circuits designed to individually control cells of said first memory cells, said second memory cells and said third memory cells,

wherein said device comprises an array of units,

wherein each of said units comprises a plurality of said first memory cells, a plurality of said second memory cells, a plurality of said third memory cells, and a portion of said memory control circuits,

wherein said array of units comprise at least eight rows and eight columns of units, and

wherein said memory control is designed to control independently each of said units.

2. The device according to claim 1,

wherein at least one of said first memory cells is self-aligned to at least one of said second memory cells.

3. The device according to claim 1,

wherein at least one of said first memory cells is self-aligned to at least one of said third memory cells.

4. The device according to claim 1,

wherein said memory cells comprise a charge trap structure or a floating gate structure.

5. The device according to claim 1,

wherein at least a portion of said memory control circuits is disposed underneath said first level or overlaying said third level.

6. The device according to claim 1, further comprising:

a feed-through conductive path through said first level, said second level and said third level.

7. The device according to claim 1,

wherein said second access pillar comprises an electrically activated contact to said second control line.

8. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first memory cells and a first control line;

a second level comprising a second array of second memory cells and a second control line;

a third level comprising a third array of third memory cells and a third control line,

wherein said second level overlays said first level, and

wherein said third level overlays said second level;

a first access pillar;

a second access pillar;

a third access pillar; and

memory control circuits designed to individually control cells of said first memory cells, said second memory cells and said third memory cells,

wherein said device comprises an array of units,

wherein each of said units comprises a plurality of said first memory cells, a plurality of said second memory cells, a plurality of said third memory cells, and a portion of said memory control circuits,

wherein said array of units comprise at least four rows and four columns of units, and

wherein said memory control is designed to control independently each of said units.

9. The device according to claim 8,

wherein at least one of said first memory cells is self-aligned to at least one of said second memory cells.

10. The device according to claim 8,

wherein at least one of said first memory cells is self-aligned to at least one of said third memory cells.

11. The device according to claim 8,

wherein said memory cells comprise a charge trap structure or a floating gate structure.

12. The device according to claim 8,

wherein at a least portion of said memory control circuits is disposed underneath said first level or overlaying said third level.

13. The device according to claim 8, further comprising:

a feed-through conductive path through said first level, said second level and said third level.

14. The device according to claim 8,

wherein said second access pillar comprises an electrically activated contact to said second control line.

15. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first memory cells,

a second level comprising a second array of second memory cells,

a third level comprising a third array of third memory cells,

wherein said second level overlays said first level, and

wherein said third level overlays said second level; and

memory control circuits designed to individually control cells of said first memory cells, said second memory cells and said third memory cells,

wherein said device comprises an array of units,

wherein each of said units comprises a plurality of said first memory cells, a plurality of said second memory cells, a plurality of said third memory cells, and a portion of said memory control circuits,

wherein said array of units comprises at least four rows and four columns of units, and

wherein said memory control is designed to control independently each of said units.

16. The device according to claim 15,

wherein at least one of said first memory cells is self-aligned to at least one of said third memory cells.

17. The device according to claim 15,

wherein said memory cells comprise a charge trap structure or a floating gate structure.

18. The device according to claim 15,

wherein at least a portion of said memory control circuits is disposed underneath said first level or overlaying said third level.

19. The device according to claim 15, further comprising:

a feed-through conductive path through said first level, said second level and said third level.

20. The device according to claim 15, further comprising:

a plurality of access pillars,

wherein said second level comprises a second control line, and

wherein at least one of said access pillars comprises an electrically activated contact to said second control line.