Transistor and display device

• US 10,418,384 B2
• Filed: 04/19/2018
• Issued: 09/17/2019
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sasaki, Toshinari, Sakata, Junichiro, Tsubuku, Masashi
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/957,318
• Publication Number:
  US 20180342538A1
• Time in Patent Office: 516 Days
• Field of Search: None
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor layer;

performing a first heat treatment at a temperature equal to or higher than 400°

C.;

forming an oxide insulating layer over and in contact with the oxide semiconductor layer;

performing a second heat treatment after forming the oxide insulating layer at a temperature equal to or higher than 200°

C. and equal to or lower than 400°

C.;

etching part of the oxide insulating layer so that the etched oxide insulating layer covers an edge portion of the oxide semiconductor layer; and

forming a source electrode and a drain electrode over the oxide insulating layer, wherein the source electrode and the drain electrode are in direct contact with the oxide semiconductor layer.

2. The method according to claim 1, wherein the first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer.

3. The method according to claim 1, wherein oxygen is supplied from the oxide insulating layer to the oxide semiconductor layer by the second heat treatment.

4. The method according to claim 1, further comprising:

forming an insulating layer over the source electrode and the drain electrode.

5. The method according to claim 4, further comprising:

forming an electrode over the insulating layer.

6. The method according to claim 5, further comprising:

forming an EL layer over and in contact with the electrode,

wherein the electrode is electrically connected with one of the source electrode and the drain electrode.

7. The method according to claim 1, wherein the edge portion of the oxide semiconductor layer is in an oxygen-excess state by oxygen supplied from the oxide insulating layer.

8. The method according to claim 1, wherein the oxide semiconductor layer comprises indium.

9. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor layer;

performing a first heat treatment to the oxide semiconductor layer;

forming an insulating layer over the oxide semiconductor layer after performing the first heat treatment;

performing a second heat treatment on the insulating layer and the oxide semiconductor layer;

etching part of the insulating layer so that the etched insulating layer covers an edge portion of the oxide semiconductor layer; and

forming an electrode layer over the insulating layer,

wherein the maximum temperature of the second heat treatment is equal to or higher than 200°

C. and equal to or lower than 400°

C.,

wherein the maximum temperature of the first heat treatment is equal to or higher than the maximum temperature of the second heat treatment, and

wherein the electrode layer is in direct contact with the oxide semiconductor layer.

10. The method according to claim 9, wherein the oxide semiconductor layer comprises indium.

11. The method according to claim 9, wherein concentration of hydrogen in the oxide semiconductor layer is reduced and oxygen vacancies are increased by the first heat treatment.