Semiconductor device and method for manufacturing the semiconductor device

• US 10,418,441 B2
• Filed: 03/15/2016
• Issued: 09/17/2019
• Est. Priority Date: 12/16/2013
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/071,185
• Publication Number:
  US 20160197143A1
• Time in Patent Office: 1,281 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A plurality of trenches is provided in a stripe shape extending in a direction parallel to a substrate front surface to a predetermined depth in a depth direction. A gate electrode is provided inside each trench, with a gate insulating film interposed there between. In mesa regions separated by the trenches, p-Type base regions at an emitter potential are provided over the entire surface layer on the substrate front surface side. Inside the p-type base regions, n⁺-type emitter regions are provided dispersedly at a predetermined interval in the longitudinal direction of the trenches. A p-type collector layer and an n⁺-type buffer layer are provided in this order on the surface layer of the substrate back surface. The thickness of the n⁺-type buffer layer is substantially equal to or larger than the thickness of an n⁻-type drift layer. As a result, switching losses are reduced while maintaining an ON voltage.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate including a first semiconductor layer of a first conductivity type;

a plurality of trenches separated respectively by a plurality of mesa regions provided in a stripe shape extending in a direction parallel to one surface of the first semiconductor layer, the plurality of trenches being provided to a predetermined depth in a depth direction from the one surface of the first semiconductor layer;

first semiconductor regions of a second conductivity type that are provided over an entire surface layer on the one surface of the first semiconductor layer to a depth which is less than that of the plurality of trenches, in respective mesa regions of the plurality of mesa regions separated by respective trenches of the plurality of trenches in the surface layer on the one surface of the first semiconductor layer;

second semiconductor regions of the first conductivity type that are selectively provided inside the first semiconductor regions;

third semiconductor regions of the second conductivity type, provided linearly in a first direction in which the plurality of trenches extend in a stripe shape;

a first electrode provided inside each trench of the plurality of trenches, with a gate insulating film interposed respectively there between;

a second semiconductor layer of the first conductivity type that is provided on a surface layer on another surface of the first semiconductor layer and that has an impurity concentration which is higher than that of the first semiconductor layer;

a third semiconductor layer of the second conductivity type that is provided in contact with the second semiconductor layer at a position which is shallower than that of the second semiconductor layer in the surface layer on the other surface of the first semiconductor layer;

a second electrode that is in contact with the first semiconductor regions and the second semiconductor regions; and

a third electrode that is in contact with the third semiconductor layer,

wherein the second semiconductor layer has a thickness that is larger than that of a portion of the first semiconductor layer that is enclosed by each of the first semiconductor regions and the second semiconductor layer, and

wherein

the second semiconductor regions are provided between adjacent trenches at a predetermined interval in the first direction and have recessed portions facing the third semiconductor regions on a side of the third electrode, and

the third semiconductor regions have a striped shape extending in the first direction and are at least partly within the recessed portions, and have a depth greater than a depth of the second semiconductor regions on sides of the recessed portions.

2. The semiconductor device according to claim 1, wherein portions of the first semiconductor regions that are enclosed between the second semiconductor regions adjacent respectively thereto in the first direction are covered with an insulating layer that covers the one surface of the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein the third semiconductor regions of the second conductivity type are selectively provided inside the first semiconductors regions and have an impurity concentration which is higher than that of the first semiconductor regions.

4. The semiconductor device according to claim 1, wherein the first semiconductor region has a thickness (a), a portion of the first semiconductor layer which is enclosed by the first semiconductor region and the second semiconductor layer has a thickness (b), the second semiconductor layer has a thickness (c), and the third semiconductor layer has a thickness (d), and wherein a sum total of thicknesses (a)+(b)+(c)+(d) is 35 μ

m to 60 μ

m inclusive.

5. The semiconductor device according to claim 1, wherein the second semiconductor layer has a thickness ranging from 15 μ

m to 30 μ

m inclusive.

6. The semiconductor device according to claim 1, wherein the third semiconductor regions of the second conductivity type have an impurity concentration higher than that of the first semiconductor regions.

7. The semiconductor device according to claim 6, wherein the third semiconductor regions has a depth of 0.5 μ

m or more.

8. The semiconductor device according to claim 6, wherein the third semiconductor regions have a depth that is greater than that of the second semiconductor regions, and the depth of the third semiconductor regions and the depth of the second semiconductor regions have a difference ranging from 0.0 μ

m to 0.3 μ

m inclusive.

9. The semiconductor device according to claim 1, wherein sides of the second semiconductor regions are connected by connecting portions, and upper surfaces of the third semiconductor regions at least partly within the recessed portions are in contact with the connecting portions.

10. The semiconductor device according to claim 1, wherein lower surfaces of the recessed portions of the second semiconductor regions contact the third semiconductor regions at a substantially central portion, in a cross-sectional view, of each of the third semiconductor regions.

11. The semiconductor device according to claim 1, wherein each recessed portion of the recessed portions is formed by side portions and a center portion of a second semiconductor region of the second semiconductor regions, the center portion extending across an uppermost surface of a corresponding third semiconductor region of the third semiconductor regions, and each of the side portions having a depth greater than a depth of the center portion.

12. A semiconductor device, comprising:

a semiconductor substrate including a first semiconductor layer of a first conductivity type;

a plurality of trenches separated respectively by a plurality of mesas provided in a stripe shape extending in a direction parallel to one surface of the first semiconductor layer, the plurality of trenches provided to a predetermined depth in a depth direction from the one surface of the first semiconductor layer;

first semiconductor regions of a second conductivity type provided over an entire surface layer on the one surface of the first semiconductor layer to a depth which is less than that of the trenches, in the plurality of mesa regions separated by respective trenches of the plurality of trenches in the surface layer on the one surface of the first semiconductor layer;

second semiconductor regions of the first conductivity type selectively provided inside the first semiconductor regions;

a first electrode provided inside each trench of the plurality of trenches, with a gate insulating film interposed there between;

a second semiconductor layer of the first conductivity type provided on a surface layer on another surface of the first semiconductor layer and having an impurity concentration which is higher than that of the first semiconductor layer;

a third semiconductor layer of the second conductivity type provided in contact with the second semiconductor layer at a position which is shallower than that of the second semiconductor layer in the surface layer on the other surface of the first semiconductor layer;

a second electrode in contact with the first semiconductor regions and the second semiconductor regions; and

a third electrode that is in contact with the third semiconductor layer, wherein

the second semiconductor layer has;

a first first-conductivity-type semiconductor layer disposed at a position apart from the third semiconductor layer that has an impurity concentration which is lower than that of the third semiconductor layer; and

a second first-conductivity-type semiconductor layer disposed between the third semiconductor layer and the first first-conductivity-type semiconductor layer and having an impurity concentration which is lower than that of the third semiconductor layer and which higher than that of the first first-conductivity-type semiconductor layer, wherein

the first first-conductivity-type semiconductor layer includes a plurality of stages greater than two, formed at respective different depths with respect to the third electrode, and

between any two of the plurality of stages, the one closer to the second first-conductivity-type semiconductor layer has a peak impurity concentration that is higher than that of the other, and has a thickness that is no smaller than that of the other.

13. The semiconductor device according to claim 12, wherein the first first-conductivity-type semiconductor layer is doped with protons.

14. The semiconductor device according to claim 12, wherein the third semiconductor layer and the third electrode have an interface, and wherein the first first-conductivity-type semiconductor layer is disposed so as to include a region at a depth of at least 2.0 μ

m to 8.0 μ

m inclusive from the interface between the third semiconductor layer and the third electrode.

15. The semiconductor device according to claim 12, wherein the second first-conductivity-type semiconductor layer is doped with phosphorus.

16. The semiconductor device according to claim 12, wherein the third semiconductor layer and the third electrode have an interface, and wherein the second first-conductivity-type semiconductor layer is disposed within a depth range of 0.5 μ

m to 3.0 μ

m inclusive from the interface between the third semiconductor layer and the third electrode.

17. The semiconductor device according to claim 12, wherein the first semiconductor region has a thickness (a), a portion of the first semiconductor layer which is enclosed by the first semiconductor region and the second semiconductor layer has a thickness (b), the second semiconductor layer has a thickness (c), and the third semiconductor layer has a thickness (d), and wherein a sum total of thicknesses (a)+(b)+(c)+(d) is 60 μ

m or less.

18. The semiconductor device according to claim 12, wherein each of the plurality of stages is in contact with another of the plurality of stages.