Semiconductor device and method for manufacturing the semiconductor device
First Claim
1. A semiconductor device, comprising:
- a semiconductor substrate including a first semiconductor layer of a first conductivity type;
a plurality of trenches separated respectively by a plurality of mesa regions provided in a stripe shape extending in a direction parallel to one surface of the first semiconductor layer, the plurality of trenches being provided to a predetermined depth in a depth direction from the one surface of the first semiconductor layer;
first semiconductor regions of a second conductivity type that are provided over an entire surface layer on the one surface of the first semiconductor layer to a depth which is less than that of the plurality of trenches, in respective mesa regions of the plurality of mesa regions separated by respective trenches of the plurality of trenches in the surface layer on the one surface of the first semiconductor layer;
second semiconductor regions of the first conductivity type that are selectively provided inside the first semiconductor regions;
third semiconductor regions of the second conductivity type, provided linearly in a first direction in which the plurality of trenches extend in a stripe shape;
a first electrode provided inside each trench of the plurality of trenches, with a gate insulating film interposed respectively there between;
a second semiconductor layer of the first conductivity type that is provided on a surface layer on another surface of the first semiconductor layer and that has an impurity concentration which is higher than that of the first semiconductor layer;
a third semiconductor layer of the second conductivity type that is provided in contact with the second semiconductor layer at a position which is shallower than that of the second semiconductor layer in the surface layer on the other surface of the first semiconductor layer;
a second electrode that is in contact with the first semiconductor regions and the second semiconductor regions; and
a third electrode that is in contact with the third semiconductor layer,wherein the second semiconductor layer has a thickness that is larger than that of a portion of the first semiconductor layer that is enclosed by each of the first semiconductor regions and the second semiconductor layer, andwhereinthe second semiconductor regions are provided between adjacent trenches at a predetermined interval in the first direction and have recessed portions facing the third semiconductor regions on a side of the third electrode, andthe third semiconductor regions have a striped shape extending in the first direction and are at least partly within the recessed portions, and have a depth greater than a depth of the second semiconductor regions on sides of the recessed portions.
1 Assignment
0 Petitions
Accused Products
Abstract
A plurality of trenches is provided in a stripe shape extending in a direction parallel to a substrate front surface to a predetermined depth in a depth direction. A gate electrode is provided inside each trench, with a gate insulating film interposed there between. In mesa regions separated by the trenches, p-Type base regions at an emitter potential are provided over the entire surface layer on the substrate front surface side. Inside the p-type base regions, n+-type emitter regions are provided dispersedly at a predetermined interval in the longitudinal direction of the trenches. A p-type collector layer and an n+-type buffer layer are provided in this order on the surface layer of the substrate back surface. The thickness of the n+-type buffer layer is substantially equal to or larger than the thickness of an n−-type drift layer. As a result, switching losses are reduced while maintaining an ON voltage.
-
Citations
18 Claims
-
1. A semiconductor device, comprising:
-
a semiconductor substrate including a first semiconductor layer of a first conductivity type; a plurality of trenches separated respectively by a plurality of mesa regions provided in a stripe shape extending in a direction parallel to one surface of the first semiconductor layer, the plurality of trenches being provided to a predetermined depth in a depth direction from the one surface of the first semiconductor layer; first semiconductor regions of a second conductivity type that are provided over an entire surface layer on the one surface of the first semiconductor layer to a depth which is less than that of the plurality of trenches, in respective mesa regions of the plurality of mesa regions separated by respective trenches of the plurality of trenches in the surface layer on the one surface of the first semiconductor layer; second semiconductor regions of the first conductivity type that are selectively provided inside the first semiconductor regions; third semiconductor regions of the second conductivity type, provided linearly in a first direction in which the plurality of trenches extend in a stripe shape; a first electrode provided inside each trench of the plurality of trenches, with a gate insulating film interposed respectively there between; a second semiconductor layer of the first conductivity type that is provided on a surface layer on another surface of the first semiconductor layer and that has an impurity concentration which is higher than that of the first semiconductor layer; a third semiconductor layer of the second conductivity type that is provided in contact with the second semiconductor layer at a position which is shallower than that of the second semiconductor layer in the surface layer on the other surface of the first semiconductor layer; a second electrode that is in contact with the first semiconductor regions and the second semiconductor regions; and a third electrode that is in contact with the third semiconductor layer, wherein the second semiconductor layer has a thickness that is larger than that of a portion of the first semiconductor layer that is enclosed by each of the first semiconductor regions and the second semiconductor layer, and wherein the second semiconductor regions are provided between adjacent trenches at a predetermined interval in the first direction and have recessed portions facing the third semiconductor regions on a side of the third electrode, and the third semiconductor regions have a striped shape extending in the first direction and are at least partly within the recessed portions, and have a depth greater than a depth of the second semiconductor regions on sides of the recessed portions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A semiconductor device, comprising:
-
a semiconductor substrate including a first semiconductor layer of a first conductivity type; a plurality of trenches separated respectively by a plurality of mesas provided in a stripe shape extending in a direction parallel to one surface of the first semiconductor layer, the plurality of trenches provided to a predetermined depth in a depth direction from the one surface of the first semiconductor layer; first semiconductor regions of a second conductivity type provided over an entire surface layer on the one surface of the first semiconductor layer to a depth which is less than that of the trenches, in the plurality of mesa regions separated by respective trenches of the plurality of trenches in the surface layer on the one surface of the first semiconductor layer; second semiconductor regions of the first conductivity type selectively provided inside the first semiconductor regions; a first electrode provided inside each trench of the plurality of trenches, with a gate insulating film interposed there between; a second semiconductor layer of the first conductivity type provided on a surface layer on another surface of the first semiconductor layer and having an impurity concentration which is higher than that of the first semiconductor layer; a third semiconductor layer of the second conductivity type provided in contact with the second semiconductor layer at a position which is shallower than that of the second semiconductor layer in the surface layer on the other surface of the first semiconductor layer; a second electrode in contact with the first semiconductor regions and the second semiconductor regions; and a third electrode that is in contact with the third semiconductor layer, wherein the second semiconductor layer has; a first first-conductivity-type semiconductor layer disposed at a position apart from the third semiconductor layer that has an impurity concentration which is lower than that of the third semiconductor layer; and a second first-conductivity-type semiconductor layer disposed between the third semiconductor layer and the first first-conductivity-type semiconductor layer and having an impurity concentration which is lower than that of the third semiconductor layer and which higher than that of the first first-conductivity-type semiconductor layer, wherein the first first-conductivity-type semiconductor layer includes a plurality of stages greater than two, formed at respective different depths with respect to the third electrode, and between any two of the plurality of stages, the one closer to the second first-conductivity-type semiconductor layer has a peak impurity concentration that is higher than that of the other, and has a thickness that is no smaller than that of the other. - View Dependent Claims (13, 14, 15, 16, 17, 18)
-
Specification