Silicon carbide semiconductor device

• US 10,418,476 B2
• Filed: 05/16/2017
• Issued: 09/17/2019
• Est. Priority Date: 07/02/2014
• Status: Active Grant

• Current Assignee: Shanghai Hestia Power Inc.
• Original Assignee: Hestia Power, Inc.
• Inventors: Yen, Cheng-Tyng, Hung, Chien-Chung, Lee, Chwan-Ying
• Primary Examiner(s): Swanson, Walter H
• Assistant Examiner(s): Ly, Kien C
• Application Number:
  US15/596,782
• Publication Number:
  US 20170250275A1
• Time in Patent Office: 854 Days
• Field of Search: None
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.

Claims

1. A silicon carbide semiconductor device, comprising:

an n-type heavily doped substrate;

an n-type drift layer disposed on the substrate, having a first doping concentration;

a plurality of doped regions disposed and spaced apart in the n-type drift layer, wherein a first junction field-effect region is formed between the doped regions, and each of the doped regions comprises a p-type well, an n-type heavily doped region disposed in the p-type well, a plurality of p-type heavily doped regions abutting the n-type heavily doped region and overlapping with a portion of the p-type well, and at least one second junction field-effect region enclosed by the p-type well;

a gate dielectric disposed on the n-type drift layer;

a gate electrode disposed on the gate dielectric;

an interlayer dielectric disposed on the gate dielectric and the gate electrode;

a plurality of source openings passing through the interlayer dielectric and the gate dielectric until a portion of the n-type heavily doped region and a portion of the p-heavily doped region are reached;

a plurality of junction openings passing through the interlayer dielectric and the gate dielectric until the second junction field-effect region, a portion of the p-type well and a portion of the p-type heavily doped region are reached;

a plurality of gate openings passing through the interlayer dielectric to the gate electrode;

a first metal layer disposed at the bottom side of the source opening to form an ohmic contact area contacting with a portion of the n-type heavily doped region and a portion of the p-type heavily doped region; and

a second metal layer comprising a first portion and a second portion, wherein the first portion covers the source openings and is electrically connected to the first metal layer;

the first portion covers the junction openings to form a Schottky contact area contacting with the second junction field-effect region; and

the second portion covers the gate openings and is electrically insulated from the first portion;

wherein the Schottky contact area is completely encircled by the n-type heavily doped region and the junction openings on a plane parallel to the bottom side of the source opening and separated by the source openings.

2. The silicon carbide semiconductor device as recited in claim 1, a distance between an edge of the n-type heavily doped region and an edge of the first junction field-effect region has a first length;

and a distance between an edge of the n-type heavily doped region and an edge of the second junction field-effect region has a second length, wherein the second length is equal to or greater than the first length.

3. The silicon carbide semiconductor device as recited in claim 1, wherein the first junction field-effect region has a second doping concentration and the second junction field-effect region has a third doping concentration;

and the second doping concentration and the third doping concentration are greater than or equal to the first doping concentration respectively.

4. The silicon carbide semiconductor device as recited in claim 3, wherein the second doping concentration and the third dopant concentration are both less than 1E18 cm⁻

3.

5. The silicon carbide semiconductor device as recited in claim 1, wherein the first doping concentration is less than 5E17 cm⁻

3.

6. The silicon carbide semiconductor device as recited in claim 1, wherein the p-type well has a first depth, the first junction field-effect region has a second depth and the second junction field-effect region has a third depth;

wherein the second depth and the third depth are greater than or equal to the first depth respectively.

7. The silicon carbide semiconductor device as recited in claim 1, wherein the first metal layer comprises a silicide containing nickel.

8. The silicon carbide semiconductor device as recited in claim 1, wherein the material of the second metal layer is selected from the group consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, aluminum-copper alloy and aluminum-silicon-copper alloy.

9. The silicon carbide semiconductor device as recited in claim 1, wherein the n-type heavily doped region comprises a plurality of adjacent peripheral portions in a continuous form, the second junction field-effect region is formed inside the peripheral portion, and the p-type heavily doped region is formed between the peripheral portion.

10. The silicon carbide semiconductor device as recited in claim 1, wherein the n-type heavily doped region comprises a plurality of peripheral portions disposed and spaced apart in a discontinuous form, the second junction field-effect region is formed inside the peripheral portion and the p-type heavily doped region is formed between the peripheral portion s to set the peripheral portion s apart.