Non-planar gate all-around device and method of fabrication thereof

• US 10,418,487 B2
• Filed: 11/19/2015
• Issued: 09/17/2019
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Sony Group Corp.
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Pillarisetty, Ravi, Le, Van H., Kavalieros, Jack T., Chau, Robert S., Kachian, Jessica S.
• Primary Examiner(s): Prenty, Mark V
• Application Number:
  US14/946,744
• Publication Number:
  US 20160079422A1
• Time in Patent Office: 1,398 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a first material, the first material having a first lattice constant;

a source region above the substrate the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;

a drain region above the substrate, the drain region comprising the second material;

a nanowire, the nanowire being coupled to the source region and being coupled to the drain region, the nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant, wherein the source region and the drain region provide a uniaxial stress to the nanowire;

a gate dielectric layer around at least a portion of the nanowire, wherein the gate dielectric layer is directly on the third material of the nanowire; and

a gate electrode around at least a portion of the nanowire and, the gate electrode being separated from the nanowire by at least the gate dielectric layer.

2. The device of claim 1, wherein the second lattice constant is larger than the first lattice constant.

3. The device of claim 1, wherein the second material is the same as the third material.

4. The device of claim 1, wherein the source region and the drain region both have side walls that are angled.

5. The device of claim 1, wherein the source region has a first width at a first position above the substrate, the source region has a second width at a second position above the substrate;

the second position being a different distance from the substrate than the first position; and

the first width is greater than the second width.

6. The device of claim 5, wherein the first width of the source is greater than a maximum width of the first nanowire.

7. The device of claim 1, further comprising an isolation region over a first portion of the substrate;

wherein a second portion of the substrate extends up past a bottom surface of the isolation region.

8. The device of claim 7, wherein the second portion of the substrate does not extend up to a top surface of the isolation region.

9. The device of claim 7, wherein at least portions of the nanowire are directly above the second portion of the substrate, but are not in direct contact with the second portion of the substrate.

10. The device of claim 1, wherein the drain region has a side wall, the side wall of the drain region is a <

111>

facet.

11. A semiconductor device, comprising:

a substrate having a top surface with a first lattice constant;

embedded epi source and drain regions disposed on the top surface of the substrates said embedded epi source and drain regions having a second lattice constant that is different from the first lattice constant;

a channel nanowire having a third lattice constant that is different from the first lattice constant, wherein the third lattice constant is the same as the second lattice constant, the channel nanowire coupled to the embedded epi source and drain regions, wherein the embedded epi source and drain regions provide a uniaxial stress to the channel nanowire;

a gate dielectric layer disposed on and all-around one axis of the channel nanowire, wherein the gate dielectric layer is directly on the channel nanowire having the third lattice constant; and

a gate electrode disposed on the gate dielectric layer and surrounding the one axis of the channel nanowire.

12. The semiconductor device of claim 11, wherein said epi source and drain regions are [111]-faceted.

13. The semiconductor device of claim 11, further comprising a bottom gate isolation disposed on the top surface of the substrate and under the channel nanowire wherein said bottom gate isolation has a thickness between about 100-300 Angstroms.

14. A semiconductor device, comprising:

a semiconductor substrate comprising a first material, the first material having a first lattice constant;

a source region above the substrate, the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;

a drain region above the substrate, the drain region comprising the second material, wherein the drain region has a side, the side wall of the drain region is a <

111>

facet;

a nanowire, the nanowire being coupled to the source region and being coupled to the drain region, the nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant;

a gate dielectric layer around at least a portion of the nanowire, wherein the gate dielectric layer is directly on the third material of the nanowire; and

a gate electrode around at least a portion of the nanowire and, the gate electrode being separated from the nanowire by at least the gate dielectric layer.

15. A semiconductor device comprising:

a substrate having a top surface with a first lattice constant;

embedded epi source and drain regions disposed on the top surface of the substrate;

said embedded epi source and drain regions having a second lattice constant that is different from the first lattice constant;

wherein said embedded epi source and drain regions are [111]-faceted;

a channel nanowire having a third lattice constant that is different from the first lattice constant, wherein the third lattice constant is the same as the second lattice constant, the channel nanowire coupled to the embedded epi source and drain regions;

a gate dielectric layer disposed on and all-around one axis of the channel nanowire, wherein the gate dielectric layer is directly on the channel nanowire having the third lattice constant; and

a gate electrode disposed on the gate dielectric layer and surrounding the one axis of the channel nanowire.

16. A semiconductor device comprising:

a substrate having a top surface with a first lattice constant;

embedded epi source and drain regions disposed on the top surface of the substrate, said embedded epi source and drain regions having a second lattice constant that is different from the first lattice constant;

a channel nanowire having a third lattice constant that is different from the first lattice constant, wherein the third lattice constant is the same as the second lattice constant, the channel nanowire coupled to the embedded epi source and drain regions;

a gate dielectric layer disposed on and all-around one axis of the channel nanowire, wherein the gate dielectric layer is directly on the channel nanowire having the third lattice constant;

a gate electrode disposed on the gate dielectric layer and surrounding the one axis of the channel nanowire; and

a bottom gate isolation disposed on the top surface of the substrate and under the channel nanowire wherein said bottom gate isolation has a thickness between about 100-300 Angstroms.