Duty cycle controller with calibration circuit

• US 10,418,978 B1
• Filed: 01/22/2019
• Issued: 09/17/2019
• Est. Priority Date: 01/22/2019
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: Au Yeung, Chung Fai, Chung, Gordon, Yu, Hok San
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US16/253,446
• Time in Patent Office: 238 Days
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

An integrator in a duty-cycle adjustment circuit has an adjustable charging current provided by a switched current-source array in response to configuration signals from the calibration logic. The integrator'"'"'s ramp voltage is compared to a threshold voltage by a comparator to generate an output clock. A tunable voltage reference generates a reference voltage that can be tuned by configuration signals from the calibration logic. The reference voltage is divided by a tunable voltage divider, which selects different fractions of the reference voltage for use as the threshold voltage. During calibration, calibration logic repeatedly raises the reference voltage or reduces the charging current from the switched current-source array until a peak voltage of the ramp voltage equals the reference voltage, when a zero duty onset detector detects that the output clock has stopped pulsing. The configuration signals at the zero duty onset condition are stored and used for normal operation.

Claims

1. A duty-cycle adjustor comprising:

an integrator for integrating a charging current to generate a ramp voltage having a cycle controlled by an input clock;

a switched current-source array for generating the charging current, wherein a magnitude of the charging current is selectable by first configuration signals;

a comparator that compares the ramp voltage to a threshold voltage, the comparator driving an output clock to a first logic state when the ramp voltage is above the threshold voltage, the comparator driving an output clock to a second logic state that is a logical opposite of the first logic state when the ramp voltage is below the threshold voltage;

a tunable voltage reference that generates a reference voltage, wherein a magnitude of the reference voltage is selectable by second configuration signals;

a tunable voltage divider that divides the reference voltage by a divisor to generate the threshold voltage, wherein the divisor is determined by third configuration signals;

a zero duty onset detector that examines the output clock and signals a zero duty onset condition when the output clock stops pulsing between the first logic state and the second logic state; and

a calibration controller that performs calibration by adjusting the first and second configuration signals until the zero duty onset detector signals the zero duty onset condition, the calibration controller storing the first configuration signals and the second configuration signals as a stored configuration when the zero duty onset condition is signaled;

wherein after calibration is completed, the calibration controller sends the first configuration signals from the stored configuration to the switched current-source array and sends the second configuration signals from the stored configuration to the tunable voltage reference,

whereby the charging current and the reference voltage are adjusted by calibration detecting the zero duty onset condition.

2. The duty-cycle adjustor of claim 1 wherein the integrator further comprises:

an integrating capacitor for integrating the charging current to generate the ramp voltage;

an input switch, receiving the input clock, for discharging the integrating capacitor in response to the input clock.

3. The duty-cycle adjustor of claim 2 wherein during calibration the calibration controller sets the third configuration signals to set the divisor to 1;

wherein the threshold voltage equals the reference voltage during calibration.

4. The duty-cycle adjustor of claim 3 wherein during calibration the calibration controller successively adjusts the first configuration signals to successively reduce the charging current until the zero duty onset condition is signaled,

wherein the charging current is successively reduced during calibration.

5. The duty-cycle adjustor of claim 4 wherein during calibration the calibration controller adjusts the second configuration signals to increase the reference voltage when the charging current reaches a minimum setting for the charging current,

wherein the reference voltage is increased during calibration when the charging current reaches the minimum setting.

6. The duty-cycle adjustor of claim 5 wherein the switched current-source array further comprises:

a plurality of array current sources that generate a plurality of array currents;

a plurality of array switches, coupled between the plurality of array current sources and an integrator node, the plurality of array switches for selecting currents in the plurality of array currents to be merged together to form the charging current;

wherein the first configuration signals control the plurality of array switches to adjust the charging current;

wherein the plurality of array switches, the integrating capacitor, and the input switch are connected together at the integrator node;

wherein the ramp voltage is a voltage of the integrator node.

7. The duty-cycle adjustor of claim 6 wherein the integrator node is directly connected to an input of the comparator to conduct the ramp voltage to the comparator.

8. The duty-cycle adjustor of claim 6 wherein the tunable voltage reference further comprises:

a plurality of current sources that receive a bias voltage, wherein the bias voltage controls current sourced by the plurality of current sources; and

a plurality of switches to connect currents generated by the plurality of current sources to a reference node;

wherein the reference node connects the tunable voltage reference to the tunable voltage divider;

wherein currents from the plurality of current sources that are selected by the plurality of switches are combined at the reference node and flow through the tunable voltage divider;

wherein a voltage of the reference node is the reference voltage.

9. The duty-cycle adjustor of claim 8 wherein the tunable voltage reference further comprises:

a band gap reference for generating the bias voltage that is relatively independent of temperature and supply-voltage variations;

wherein the bias voltage controls current sourced by the plurality of current sources.

10. The duty-cycle adjustor of claim 9 wherein the tunable voltage divider further comprises:

a plurality of resistors that are connected in series between the reference node an a ground;

a plurality of tap nodes between adjacent resistors in the plurality of resistors; and

a mux having the plurality of tap nodes and the reference node as mux inputs, controlled by the third configuration signals that select one of the mux inputs to output as the threshold voltage.

11. The duty-cycle adjustor of claim 10 wherein the third configuration signals set a target duty cycle of the output clock, the target duty cycle being adjusted by calibration to compensate for variations in temperature, supply voltage, and process.

12. The duty-cycle adjustor of claim 11 wherein the input clock has a 50% duty cycle;

wherein the comparator further comprises a complementary output that generates a complementary output clock that is a logical inverse of the output clock;

wherein the output clock is selected for use by a downstream device when a target duty cycle is less than 50%;

wherein the complementary output clock is selected for use by the downstream device when the target duty cycle is more than 50%.

13. The duty-cycle adjustor of claim 11 wherein the input clock is a clock for synchronizing an input video stream;

wherein the output clock is a tuned clock for re-synchronizing the input video stream;

wherein video timing errors are reduced by using the tuned clock.

14. A method for calibrating a duty-cycle controller comprising:

configuring a tunable voltage reference to generate a reference voltage having a minimum value;

configuring a tunable voltage divider to pass the reference voltage through to a threshold voltage;

configuring a switched current-source array to generate a charging current having a maximum value;

operating an integrator to charge a capacitor using the charging current and to discharge the capacitor in response to an input clock to generate a ramp voltage;

comparing the ramp voltage to the threshold voltage and driving an output clock to a first state when the ramp voltage is less than the threshold voltage, and driving the output clock to a second state when the ramp voltage is less than the threshold voltage;

monitoring the output clock and signaling a zero duty onset condition when the output clock stops pulsing between the first state and the second state;

when the zero duty onset condition is not yet signaled, successively reducing the charging current until a minimum charging current is reached;

when the zero duty onset condition is not yet signaled and the minimum charging current is reached, successively increasing the reference voltage;

when the zero duty onset condition is not yet signaled and the minimum charging current is reached, and a maximum of the reference voltage is reached, signaling a calibration limit;

when the zero duty onset condition is signaled, storing a configuration setting of the switched current-source array and of the tunable voltage reference and using this configuration setting for operation of the duty-cycle controller to generate the output clock; and

when the zero duty onset condition is signaled, applying a target configuration setting for the tunable voltage divider that causes the tunable voltage divider to divide the reference voltage by a divisor K to generate the threshold voltage, wherein K is more than one, wherein the target configuration setting determines a target duty cycle for the output clock.

15. The method of claim 14 wherein configuring the tunable voltage reference further comprises applying first configuration signals generated by calibration logic to the tunable voltage reference, the first configuration signals determining a tunable current to the tunable voltage divider.

16. The method of claim 15 wherein configuring the switched current-source array further comprises applying second configuration signals generated by calibration logic to the switched current-source array, the second configuration signals determining the charging current generated by the switched current-source array and applied to the integrator.

17. The method of claim 16 wherein monitoring the output clock and signaling the zero duty onset condition when the output clock stops pulsing between the first state and the second state comprises:

using the output clock to latch a pre-determined signal into a first flip-flop;

using a delayed input clock to reset the first flip-flop;

using the input clock to clock an output of the first flip-flop into a second flip-flop; and

signaling the zero duty onset condition when an output of the second flip-flop changes between the first state and the second state.

18. A selectable duty-cycle clock generator comprising:

a voltage ramp generator that generates a ramp voltage having a triangular waveform that is synchronized to an input clock;

a signal strength adjuster that adjusts a peak voltage of the ramp voltage in response to first configuration signals;

a comparator that compares the ramp voltage to a threshold voltage to generate an output clock;

a tunable voltage reference that generates a reference voltage determined by second configuration signals;

a tunable voltage divider that dividers the reference voltage to generate the threshold voltage, the tunable voltage divider dividing the reference voltage by an amount determined by third configuration signals;

a zero duty detector for detecting a calibration endpoint when the output clock has a zero duty cycle wherein pulses of the output clock have an insufficient pulse width to meet timing requirements; and

calibration logic that receives a target duty cycle and drives the third configuration signals with a value causing the output clock to have the target duty cycle during a normal operation mode;

wherein the calibration logic further comprising means for performing a calibration routine to generate a calibrated set of the first and second calibration signals that cause the zero duty cycle to detect the calibration endpoint;

wherein the calibration logic applies the calibrated set of the first calibration signals to the signal strength adjuster and applies the calibrated set of the second calibration signals to the tunable voltage reference during the normal operation mode;

whereby the target duty cycle is calibrated.

19. The selectable duty-cycle clock generator of claim 18 wherein the calibration logic drives the third configuration signals to a calibration value that causes the tunable voltage divider to drive the reference voltage to the comparator in place of the threshold voltage during the calibration routine;

wherein the ramp voltage is calibrated to the reference voltage during the calibration routine while the ramp voltage is compared to the threshold voltage during the normal operation mode.

20. The selectable duty-cycle clock generator of claim 19 wherein the voltage ramp generator further comprises:

an integrating capacitor that generates the ramp voltage on an integrating node;

a discharge switch for discharging the integrating capacitor in response to the input clock;

wherein the signal strength adjuster further comprises;

a switched current-source array having a plurality of current sources that are selectively enabled by the first configuration signals to adjust a charging current to the integrating capacitor.