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SM4 acceleration processors, methods, systems, and instructions

  • US 10,419,210 B2
  • Filed: 07/02/2018
  • Issued: 09/17/2019
  • Est. Priority Date: 07/22/2014
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a data cache;

    a data translation lookaside buffer (TLB) coupled to the data cache;

    a branch prediction unit;

    an instruction cache;

    an instruction TLB coupled to the instruction cache;

    an instruction fetch unit to fetch instructions, including an instruction;

    a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache;

    a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four source data elements to be encrypted with an SM4 cryptographic algorithm, the second register to store a second source data that includes four round keys, wherein the plurality of registers are dynamically allocated using register renaming;

    a decoder to decode the instruction, the instruction having a first field to specify the first register, and a second field to specify the second register; and

    an execution unit coupled to the decoder, and coupled to the plurality of registers, the execution unit including at least some circuitry, and, in response to the instruction, to generate and store a result in the first register, the result to include four result data elements that include the first source data encrypted by four corresponding encryption rounds of the SM4 cryptographic algorithm, wherein the execution unit is to generate each of the four result data elements to be consistent with an evaluation of a linear substitution function with a value for the corresponding encryption round, which is equal to the value logically XOR'"'"'d with the value rotated left by two bits logically XOR'"'"'d with the value rotated left by ten bits logically XOR'"'"'d with the value rotated left by eighteen bits logically XOR'"'"'d with the value rotated left by twenty-four bits.

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