Devices, systems, and methods for increasing endurance on a storage system having a plurality of components using adaptive code-rates

• US 10,423,345 B2
• Filed: 09/06/2017
• Issued: 09/24/2019
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Smart IOPS, Inc.
• Original Assignee: Smart IOPS, Inc.
• Inventors: d'Abreu, Manuel Antonio
• Primary Examiner(s): McMahon, Daniel F.
• Application Number:
  US15/732,039
• Publication Number:
  US 20180067666A1
• Time in Patent Office: 748 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Devices, systems, and methods are provided that include a controller configured to receive a first data packet from a memory device; determine a bit error count for the first data packet; and determine whether the bit error count exceeds a predetermined threshold. When the bit error count exceeds the predetermined threshold, the controller corrects errors identified in the bit error count; generates and inserts pre-defined data into the first data packet at a location where errors occurred in the first data packet; and generates and inserts a tag into the first data packet. The tag includes information indicating a size and a location of the pre-defined data in the first data packet.

Claims

1. A data storage device, comprising:

a memory device comprising one or more memory dies; and

a controller communicatively coupled to the memory device, the controller comprising hardware logic and configured to;

receive a first data packet from the memory device, the first data packet comprising data from a first one or more wordlines in the memory device;

compute a bit error count for errors identified in the first data packet;

determine whether the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correct the errors identified in the first data packet;

insert pre-defined data into the first one or more wordlines at a location where the errors occurred in the first data packet; and

generate a tag and insert the tag into the first one or more wordlines, the tag comprising information indicating a size and the location of the pre-defined data in the first one or more wordlines.

2. The data storage device of claim 1, wherein the first data packet comprises data from a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and the tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines, respectively.

3. The data storage device of claim 1, wherein the controller is further configured to, when the error count is determined to exceed the predetermined threshold, store raw data from the first data packet to a second one or more wordlines, wherein the second one or more wordlines is at a different location in the memory device than the first one or more wordlines, and wherein the raw data comprises the corrected errors.

4. The data storage device of claim 1, wherein the controller is further configured to:

track bit error counts for the first one or more wordlines; and

reset the bit error count for the first one or more wordlines after the pre-defined data and the tag are inserted into the first one or more wordlines.

5. The data storage device of claim 1, wherein the tag further comprises decoding instructions.

6. The data storage device of claim 1, wherein the pre-defined data is a pattern of all 1'"'"'s or 0'"'"'s.

7. The data storage device of claim 1, wherein the controller is further configured to, when the bit error count is determined to not exceed the predetermined threshold:

correct the errors identified in the first data packet; and

update the bit error count for the first one or more wordlines.

8. The data storage device of claim 1, wherein the predetermined threshold is a rate of increase of bit error counts, and wherein the bit error count is determined to exceed the predetermined threshold based on a comparison to a previous bit error count for the first one or more wordlines.

9. The data storage device of claim 1, wherein the memory device comprises a three-dimensional (3D) memory configuration.

10. The data storage device of claim 1, wherein the controller is further configured to:

classify one or more health levels for the first one or more wordlines;

maintain profile information for the the first one or more wordlines, the profile information comprising bit error counts for the the first one or more wordlines; and

determine the predetermined threshold for the first data packet based on the health level classifications for the first one or more wordlines.

11. A system, comprising:

a data storage device comprising;

a memory device comprising one or more memory dies; and

a controller communicatively coupled to the memory device, the controller comprises hardware logic and configured to;

receive a first data packet from the memory device, the first data packet comprising data from a first one or more wordlines in the memory device;

compute a bit error count for errors identified in the first data packet;

determine whether the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correct the errors identified in the first data packet;

insert pre-defined data into the first one or more wordlines at a location where the errors occurred; and

generate a tag and insert the tag into the first one or more wordlines, the tag comprising information indicating a size and the location of the pre-defined data in the first one or more wordlines; and

an accessing device communicatively coupled to the data storage device, wherein the accessing device is configured to issue commands to the data storage device to perform read and write operations on the memory device.

12. The system of claim 11, wherein the first data packet comprises data from a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and the tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines, respectively.

13. The system of claim 11, wherein the controller is further configured to:

track bit error counts for the first one or more wordlines;

when the error count is determined to exceed the predetermined threshold, store raw data from the first data packet to a second one or more wordlines, wherein the second one or more wordlines is at a different location in the memory device than the first one or more wordlines, and wherein the raw data comprises the corrected errors; and

reset the bit error count for the first one or more wordlines.

14. The system of claim 11, wherein the data storage device is embedded within the accessing device.

15. A method, comprising:

receiving, by a controller comprising hardware logic, a first data packet from a memory device, the first data packet comprising data from a first one or more wordlines in the memory device, and the memory device communicatively coupled to the controller;

computing, by the controller, a bit error count for errors identified in the first data packet;

determining, by the controller, whether the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correcting, by the controller, the errors identified in the first data packet;

inserting, by the controller, pre-defined data into the first one or more wordlines at a location where the errors occurred; and

generating, by the controller, a tag and inserting, by the controller, the tag into the first one or more wordlines, wherein the tag comprises information indicating a size and the location of the pre-defined data in the first one or more wordlines.

16. The method of claim 15, wherein the first data packet comprises data from a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and the tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines, respectively.

17. The method of claim 15, further comprising, when the error count is determined to exceed the predetermined threshold, storing, by the controller, raw data from the first data packet to a second one or more wordlines, wherein the second one or more wordlines is at a different location in the memory device than the first one or more wordlines, and wherein the raw data comprises the corrected errors.

18. The method of claim 15, further comprising:

tracking, by the controller, bit error counts for the first one or more wordlines; and

resetting, by the controller, the bit error count for the first one or more wordlines after the pre-defined data and the tag are inserted into the first one or more wordlines.

19. The method of claim 15, wherein the tag further comprises decoding instructions.

20. The method of claim 15, wherein the pre-defined data is a pattern of all 1'"'"'s or 0'"'"'s.