Apparatus and method for predicting a redundancy period

• US 10,423,510 B2
• Filed: 10/04/2017
• Issued: 09/24/2019
• Est. Priority Date: 10/04/2017
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Ramrakhyani, Prakash S., Beard, Jonathan Curtis
• Primary Examiner(s): Mercado, Ramon A.
• Application Number:
  US15/724,433
• Publication Number:
  US 20190102272A1
• Time in Patent Office: 720 Days
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06F 9/5033 considering data affinity

Abstract

An apparatus comprises a plurality of memory units organized as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.

Claims

1. An apparatus comprising:

a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of said memory units is associated with a processor element;

predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and

an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period,

wherein said data processing operation is performed in response to execution of a given instruction from a series of instructions comprising a loop, and said prediction process is based on a processing period of one iteration of said loop.

2. An apparatus according to claim 1, wherein a relationship between an access speed of a memory unit associated with said selected processor element and said predicted redundancy period is that as said predicted redundancy period decreases, said access speed increases.

3. An apparatus according to claim 1, wherein in response to said predicted redundancy period indicating that said result data will be accessed again within a reuse period, said selected processor element is associated with a faster memory unit that can be accessed more quickly than another of said memory units and said selected processor element stores said result data in said faster memory unit.

4. An apparatus according to claim 1, wherein in response to said predicted redundancy period indicating an absence of further accesses to said result data within a reuse period, said selected processor element is a processor element associated with a slower memory unit that can be accessed less quickly than said faster memory unit and said selected processor stores said result data in said slower memory unit.

5. An apparatus according to claim 1, wherein said prediction process uses historical data.

6. An apparatus according to claim 1, wherein said prediction process uses historical data of a redundancy period of an operand of a previous data processing operation used to generate said result data.

7. An apparatus according to claim 6, wherein said historical data is a most recent redundancy period of said operand.

8. An apparatus according to claim 1, further comprising a non-saturating counter to increment during said one iteration of said loop, and a saturating counter to determine a wrap around count of said non-saturating counter, wherein said prediction process uses said wrap around count.

9. An apparatus according to claim 1, wherein said prediction processes is affected by a bias value;

and

said bias value is adjusted by comparing a previously predicted redundancy period of further result data with a redundancy period of said further result data.

10. An apparatus according to claim 9, wherein when said previously predicted redundancy period is less than said redundancy period of said result data, said bias value is adjusted to bias selection towards a processor element associated with a slower memory unit, and when said bias value indicates that said previously predicted redundancy period is greater than said redundancy period said predictor circuitry is configured to bias selection towards a processor element associated with a faster memory unit.

11. An apparatus according to claim 1, wherein said prediction processes is affected by a bias value;

said operation controller is adapted to cause a previous selected processor element to perform a previous data processing operation to produce previous result data;

said previous result data is stored in one of said plurality of memory units associated with said previous selected processor element; and

said bias value is adjusted by whether a previous access request for said previous result data hits or misses in said one of said plurality of memory units associated with said previous selected processor element.

12. An apparatus according to claim 11, wherein

said bias value is adjusted to bias selection towards a processor element associated with a slower memory unit in response to said previous access request missing.

13. An apparatus according to claim 1, wherein said data processing operation is performed as an atomic operation.

14. An apparatus according to claim 1, wherein said operation controller is configured to provide said selected processor with exclusive use of source data required to perform said data processing operation.

15. An apparatus according to claim 1, wherein said data processing operation is performed in response to one of:

a microinstruction;

an instruction;

or

a task comprising a plurality of instructions.

16. A method for use in an apparatus comprising a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of said memory units is associated with a processor element, said method comprising:

performing a prediction process to determine a predicted redundancy period of result data of a data processing operation to performed, indicating a predicted point when said result data will be next accessed; and

selecting a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period,

wherein said data processing operation is performed in response to execution of a given instruction from a series of instructions comprising a loop, and said prediction process is based on a processing period of one iteration of said loop.