Packet flow tracing in a parallel processor complex

• US 10,423,511 B2
• Filed: 11/29/2016
• Issued: 09/24/2019
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ratcliff, Bruce
• Primary Examiner(s): Kamran, Mehran
• Application Number:
  US15/362,943
• Publication Number:
  US 20180150374A1
• Time in Patent Office: 1,029 Days
• Field of Search: 718105
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/3461 Trace driven simulation
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 9/28 Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
• CPC Class Codes: H04L 43/026 using flow identification
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps

Abstract

Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.

Claims

1. A system for packet flow tracing in a parallel processor complex, the system comprising:

a memory comprising computer readable instructions; and

a processing device for executing the computer readable instructions for performing a method, the method comprising;

receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith;

creating, by the trace processor, a trace entry by allocating an element from a shared queue;

loading, by the trace processor, the trace entry into a common trace buffer; and

loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record, the interface identifier identifying the one of the plurality of task execution processors with which the trace entry is associated,

wherein the trace processor uses the interface identifier and the queue pair index record to load the trace entry into the common trace buffer, and

wherein the queue pair index record indicates to which of the plurality of trace buffers to load the trace entry.

2. The system of claim 1, wherein the element uniquely identifies the host interface and queue pair used for the element.

3. The system of claim 1, wherein the trace entry comprises a header, wherein the header comprises a processor identifier, at interface identifier, a queue pair index, a tag, a timestamp, and unique data.

4. A computer program product for packet flow tracing in a parallel processor complex, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing device to cause the processing device to perform a method comprising;

receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith;

creating, by the trace processor, a trace entry by allocating an element from a shared queue;

loading, by the trace processor, the trace entry into a common trace buffer; and

loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record, the interface identifier identifying the one of the plurality of task execution processors with which the trace entry is associated,

wherein the trace processor uses the interface identifier and the queue pair index record to load the trace entry into the common trace buffer, and

wherein the queue pair index record indicates to which of the plurality of trace buffers to load the trace entry.

5. The computer program product of claim 4, wherein the element uniquely identifies the host interface and queue pair used for the element.