Frequency allocation in multi-qubit circuits

• US 10,423,888 B1
• Filed: 06/07/2018
• Issued: 09/24/2019
• Est. Priority Date: 06/07/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hertzberg, Jared Barney, Rosenblatt, Sami, Magesan, Easwar, Smolin, John Aaron
• Primary Examiner(s): Ho, Tu-Tu V
• Application Number:
  US16/002,817
• Time in Patent Office: 474 Days
• Field of Search: 257 31
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H10N 99/05 Quantum devices, e.g. quantum interference devices, metal single electron transistors

Abstract

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

Claims

1. A system comprising:

a memory that stores computer executable components; and

a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise;

a yield determination component that determines an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and

a selection component that selects a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

2. The system of claim 1, wherein the computer executable components further comprise:

a configuration component that generates the respective qubit chip configurations such that the qubit chip configurations differ from each other with respect to at least one of a geometric configuration or a frequency configuration.

3. The system of claim 2, wherein the geometric configuration comprises at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus.

4. The system of claim 2, wherein the frequency configuration comprises at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits.

5. The system of claim 1, wherein the yield determination component counts frequency collisions occurring for the respective qubit chip configurations during the simulations and determines the estimated fabrication yield as a statistical probability based on counted frequency collisions over a series of simulation trials in which real-world imprecision of device parameters is approximated by a probabilistic or statistical model implemented by the yield determination component, thereby facilitating adjustment of the respective qubit chip configurations by the yield determination component to account for the frequency collisions.

6. The system of claim 5, wherein the yield determination component defines frequency collision windows for respective qubits in the respective qubit chip configurations and counts the frequency collisions according to the frequency collision windows.

7. The system of claim 1, wherein the respective qubit chip configurations include one or more of fixed-frequency qubits or tunable-frequency qubits.

8. The system of claim 1, wherein the computer executable components further comprise:

a fabrication component that fabricates a superconducting qubit chip according to the qubit chip configuration selected by the selection component, wherein the qubit chip configuration selected by the selection component results in improved resilience of the superconducting qubit chip to imperfections in fabrication by the fabrication component.

9. A computer-implemented method comprising:

determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and

selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

10. The computer-implemented method of claim 9, further comprising:

generating, by the device, the respective qubit chip configurations such that the qubit chip configurations differ from each other with respect to at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus.

11. The computer-implemented method of claim 9, further comprising:

generating, by the device, the respective qubit chip configurations such that the qubit chip configurations differ from each other with respect to at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits.

12. The computer-implemented method of claim 9, wherein the determining comprises:

counting, by the device, frequency collisions occurring for the respective qubit chip configurations during the simulations; and

determining, by the device, the estimated fabrication yield as a statistical probability based on the counting as conducted over a series of simulation trials in which real-world imprecision of device parameters is approximated by a probabilistic or statistical model.

13. The computer-implemented method of claim 12, wherein the selecting results in a selected qubit chip configuration, further comprising:

fabricating, by the device, a superconducting qubit chip according to the selected qubit chip configuration.

14. A computer program product for designing a superconducting qubit chip, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

determine an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and

select a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

15. The computer program product of claim 14, wherein the program instructions further cause the processor to:

generate the respective qubit chip configurations such that the qubit chip configurations differ from each other with respect to at least one of geometric configuration or frequency configuration.

16. The computer program product of claim 14, wherein the program instructions further cause the processor to:

count frequency collisions occurring for the respective qubit chip configurations during the simulations; and

determine the estimated fabrication yield as a statistical probability based on counted frequency collisions over a series of simulation trials in which real-world imprecision of device parameters is approximated by a probabilistic or statistical model.