Semiconductor integrated circuit including master chip and slave chip that are stacked

• US 10,424,355 B2
• Filed: 08/16/2017
• Issued: 09/24/2019
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Dong-Uk, Kim, Young-Ju, Song, Keun-Soo
• Primary Examiner(s): Lam, David
• Application Number:
  US15/678,662
• Publication Number:
  US 20170365312A1
• Time in Patent Office: 769 Days
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1054 Optical output buffers
• CPC Class Codes: G11C 7/1081 Optical input buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Claims

1. A semiconductor integrated circuit including at least one master chip and at least one slave chip that are stacked,

the master chip being configured to transmit write data and differential write strobe signals source-synchronized with the write data, to the slave chip based on a first internal rising strobe signal and a first internal falling strobe signal, and receive and output read data transmitted from the slave chip, based on first differential alignment strobe signals which are provided from the slave chip and are generated by delaying differential read strobe signals source-synchronized with the read data, by a given delay time, and

the slave chip being configured to transmit the read data and the differential read strobe signals, to the master chip in based on a second internal rising strobe signal and a second internal falling strobe signal, and store therein the write data transmitted from the master chip, based on second differential alignment strobe signals which are generated by delaying the differential write strobe signals by the given delay time.

2. The semiconductor integrated circuit of claim 1, wherein the master chip receives the read data in synchronization with given edges of the first differential strobe signals, and wherein the slave chip receives the write data in synchronization with given edges of the second differential strobe signals.

3. The semiconductor integrated circuit of claim 1, wherein the master chip comprises:

at least one first write data driving circuit configured to transmit the respective write data transmitted through at least one pair of middle input/output lines, to the slave chip in a DDR scheme based on the first internal rising strobe signal, the first internal falling strobe signal, and a write enable signal;

a write strobe signal driving circuit configured to generate the write strobe signals based on the first internal strobe signal and the write enable signal, and transmit the write strobe signals to the slave chip;

a first read data driving circuit configured to load the respective read data transmitted in the DDR scheme from the slave chip, on the pair of middle input/output lines based on the first alignment strobe signals and an inverted write enable signal; and

a first differential alignment strobe signal driving circuit configured to generate the first differential alignment strobe signals by delaying the differential read strobe signals transmitted from the slave chip by the given delay time based on the inverted write enable signal and a first delay control signal.

4. The semiconductor integrated circuit of claim 3, wherein the first differential alignment strobe signal driving circuit comprises:

a first rising alignment strobe signal driving circuit configured to output a first rising alignment strobe signal corresponding to a rising read strobe signal of the differential read strobe signals, based on the inverted write enable signal and the first delay control signal; and

a first falling alignment strobe signal driving circuit configured to output a first falling alignment strobe signal corresponding to a falling read strobe signal of the differential read strobe signals, based on the inverted write enable signal and the first delay control signal.

5. The semiconductor integrated circuit of claim 4, wherein the first rising alignment strobe signal driving circuit comprises:

a first input unit configured to receive the rising read strobe signal based on the inverted write enable signal; and

a first delay unit configured to delay the rising read strobe signal outputted from the first input unit, by the given delay time based on the first delay control signal, and output the first rising alignment strobe signal.

6. The semiconductor integrated circuit of claim 5, wherein the first rising alignment strobe signal driving circuit further comprises:

a first repeater configured to output the first rising alignment strobe signal with a given driving force.

7. The semiconductor integrated circuit of claim 4, wherein the first falling alignment strobe signal driving circuit comprises:

a second input unit configured to receive the falling read strobe signal based on the inverted write enable signal; and

a second delay unit configured to delay the falling read strobe signal outputted from the second input unit, by the given delay time based on the first delay control signal, and output the first falling alignment strobe signal.

8. The semiconductor integrated circuit of claim 7, wherein the first falling alignment strobe signal driving circuit further comprises:

a second repeater configured to output the first falling alignment strobe signal with the given driving force.

9. The semiconductor integrated circuit of claim 1, wherein the given delay time corresponds to ¼

cycle of the differential read strobe signals or the differential write strobe signals.

10. The semiconductor integrated circuit of claim 1, wherein the slave chip comprises:

at least one second read data driving circuit configured to transmit the respective read data transmitted through at least one pair of global input/output lines, to the master chip in the DDR scheme based on the second internal rising strobe signal, the second internal falling strobe signal, and a read enable signal;

a read strobe signal driving circuit configured to generate the differential read strobe signals based on the second internal rising strobe signal, the second internal falling strobe signal, and the read enable signal, and transmit the differential read strobe signals to the master chip;

a second write data driving circuit configured to load the respective write data transmitted from the master chip, on the pair of global input/output lines based on the second differential alignment strobe signals, an internal write strobe signal and an inverted read enable signal; and

a second differential alignment strobe signal driving circuit configured to generate the second differential alignment strobe signals corresponding to the differential write strobe signals, based on the inverted read enable signal and a second delay control signal.

11. The semiconductor integrated circuit of claim 10, wherein the second differential alignment strobe signal driving circuit comprises:

a second rising alignment strobe signal driving circuit configured to output a second rising alignment strobe signal corresponding to a rising write strobe signal of the differential write strobe signals, based on the inverted read enable signal and the second delay control signal; and

a second falling alignment strobe signal driving circuit configured to output a second falling alignment strobe signal corresponding to a falling write strobe signal of the differential write strobe signals, based on the inverted read enable signal and the second delay control signal.

12. The semiconductor integrated circuit of claim 11, wherein the second rising alignment strobe signal driving circuit comprises:

a third input unit configured to receive the rising write strobe signal based on the inverted read enable signal; and

a third delay unit configured to delay the rising write strobe signal outputted from the third input unit, by the given delay time based on the second delay control signal, and output the second rising alignment strobe signal.

13. The semiconductor integrated circuit of claim 12, wherein the second rising alignment strobe signal driving circuit further comprises:

a third repeater configured to output the second rising alignment strobe signal with the given driving force.

14. The semiconductor integrated circuit of claim 11, wherein the second falling alignment strobe signal driving circuit comprises:

a fourth input unit configured to receive the falling write strobe signal based on the inverted read enable signal; and

a fourth delay unit configured to delay the falling write strobe signal outputted from the fourth input unit, by the given delay time based on the second delay control signal, and output the second falling alignment strobe signal.

15. The semiconductor integrated circuit of claim 14, wherein the second falling alignment strobe signal driving circuit further comprises:

a fourth repeater configured to output the second falling alignment strobe signal with the given driving force.

16. The semiconductor integrated circuit of claim 1, wherein the given delay time corresponds to ¼

cycle of the differential write strobe signals or the differential read strobe signals.

17. The semiconductor integrated circuit of claim 1, wherein the write data and the read data are transmitted through at least one first through-chip via that vertically passes through the master chip or the slave chip, and wherein the differential write strobe signals and the differential read strobe signals are transmitted through second and third through-chip vias that vertically pass through the master chip or the slave chip.