Method of reading data from a memory device using multiple levels of dynamic redundancy registers

• US 10,424,393 B2
• Filed: 12/20/2017
• Issued: 09/24/2019
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: El Baraji, Mourad, Berger, Neal, Louie, Benjamin Stanley, Crudele, Lester M., Hillman, Daniel L., Hoberman, Barry
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US15/849,404
• Publication Number:
  US 20180114589A1
• Time in Patent Office: 643 Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.

Claims

1. A method of reading data from a memory device, the method comprising:

reading a data word from a memory array at a selected address of a plurality of memory addresses; and

responsive to a determination that the data word was not successfully read by the reading within a predetermined error threshold, writing the data word and the selected address of the plurality of memory addresses into a first level dynamic redundancy buffer.

2. The method of claim 1, wherein the memory array comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. The method of claim 1, further comprising:

responsive to a determination that the data word was not successfully read within the predetermined error threshold by the reading, attempting to correct errors in the data word using error-correcting code (ECC).

4. The method of claim 1, further comprising:

accessing the data word from the first level dynamic redundancy buffer, wherein the first level dynamic redundancy buffer comprises data words to be re-written into the memory array; and

re-writing the data word into the memory array at the selected address of the plurality of memory addresses.

5. The method of claim 4, further comprising:

performing a verification to determine if the data word was successfully written to the memory array by the re-writing; and

responsive to a determination that the data was not successfully written by the re-writing, writing the data word and the selected address of the plurality of memory addresses into a second level dynamic redundancy buffer.

6. The method of claim 5, further comprising:

remapping the data word from the second level dynamic redundancy buffer to an address in the memory array, wherein the second level dynamic redundancy buffer stores a remap address for the data word.

7. The method of claim 5, further comprising:

attempting the re-writing a predetermined number of times prior to writing the data word and the selected address of the plurality of memory addresses into the second level dynamic redundancy buffer, and wherein the predetermined number is stored using control bits associated with re-write attempts.

8. The method of claim 7, wherein the predetermined number is stored using control bits of the first level dynamic redundancy buffer.

9. The method of claim 4, wherein the re-writing is attempted during a clock cycle in which the memory array is inactive, and wherein the re-writing is attempted in the same clock cycle as a verify operation.

10. The method of claim 9, wherein the memory array comprises a pseudo-dual port memory array, wherein the pseudo-dual port memory array is operable to perform a write operation and a verify operation in a same clock cycle.

11. The method of claim 10, wherein a data word associated with the verify operation shares a common row address with the data word associated with the re-writing.

12. The method of claim 5, wherein the memory array comprises a dual port memory array, wherein the dual port memory array is operable to perform a write operation and a verify operation in a same clock cycle.

13. The method of claim 1, wherein the first level dynamic redundancy buffer comprises volatile memory.

14. The method of claim 1, wherein the first level dynamic redundancy buffer comprises non-volatile memory.

15. The method of claim 5, wherein the second level dynamic redundancy buffer comprises non-volatile memory.

16. The method of claim 5, wherein the second level dynamic redundancy buffer comprises volatile memory.

17. A method of reading data from a memory device, the method comprising:

reading a data word from a memory array at a selected address of a plurality of memory addresses, wherein the memory array is configured to store a data word at one of a plurality of memory addresses, and wherein the reading comprises;

determining if the selected address of the plurality of addresses is available in a pipeline;

responsive to a determination that the selected address of the plurality of addresses is not available in the pipeline, checking a first level dynamic redundancy buffer for the selected address of the plurality of addresses;

responsive to a determination that the selected address of the plurality of addresses is not in the first level dynamic redundancy buffer, checking a second level dynamic redundancy buffer for the selected address of the plurality of addresses; and

responsive to a determination that the selected address of the plurality of addresses is not in the second level dynamic redundancy buffer, reading the data word from the memory array at the selected address of the plurality of addresses.

18. The method of claim 17, further comprising:

responsive to a determination that the data word was not successfully read from the memory array within a predetermined error threshold by the reading, writing the data word and the selected address of the plurality of memory addresses into the first level dynamic redundancy buffer.

19. The method of claim 17, further comprising:

responsive to a determination that the selected address of the plurality of addresses is available in the pipeline, retrieving the data word from the pipeline.

20. The method of claim 17, further comprising:

responsive to a determination that the selected address of the plurality of addresses is available in the first level dynamic redundancy buffer, retrieving the data word from the first level dynamic redundancy buffer.

21. The method of claim 17, further comprising:

responsive to a determination that the selected address of the plurality of addresses is available in the second level dynamic redundancy buffer, retrieving the data word from the second level dynamic redundancy buffer.

23. The memory device of claim 21, wherein the plurality of addressable memory cells of the memory array comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

24. The memory device of claim 21, wherein the processor is further configured to:

determine the data word from the first level dynamic redundancy buffer, wherein the first level dynamic redundancy buffer comprises data words to be re-written into the memory array; and

re-write the data word into the memory array at the selected one of the plurality of memory addresses.

25. The memory device of claim 23, wherein the processor is further configured to:

perform a verification to determine if the data word was successfully written to the memory array by the re-writing; and

responsive to a determination that the data was not successfully written by the re-writing, write the data word and the selected address of the plurality of memory addresses into a second level dynamic redundancy buffer.

22. A memory device for storing data, the memory device comprising:

a memory array comprising a plurality of addressable memory cells;

a first level dynamic redundancy buffer operable for storing a plurality of data words and associated memory addresses, wherein the first level dynamic redundancy buffer is associated with the memory array, and wherein each data word of the plurality of data words is awaiting write verification associated with the memory array or is to be re-written into the memory array; and

a processor configured to;

read a data word from the memory array at a selected address of a plurality of memory addresses, wherein each of the plurality of memory addresses is configured to store a data word; and

responsive to a determination that the data word was not successfully read within a predetermined error threshold by the reading, writing the data word and the selected address of the plurality of memory addresses into the first level dynamic redundancy buffer.