Micro device stabilization post

• US 10,424,493 B2
• Filed: 02/28/2017
• Issued: 09/24/2019
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hu, Hsin-Hua, Bibl, Andreas, Higginson, John A.
• Primary Examiner(s): Gupta, Raj R
• Assistant Examiner(s): Stowe, Scott
• Application Number:
  US15/445,476
• Publication Number:
  US 20170170049A1
• Time in Patent Office: 938 Days
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/93 Batch processes
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/40 Materials therefor

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims

1. A structure comprising:

a stabilization layer comprising an array of stabilization posts;

an array of micro devices on the array of stabilization posts;

wherein each micro device is supported by a corresponding plurality of stabilization posts of the array of stabilization posts, and each micro device includes a bottom surface that is wider than the corresponding plurality of stabilization posts; and

a sacrificial layer between the stabilization layer and the array of micro devices, wherein a topography of the stabilization layer beneath the sacrificial layer conforms to the sacrificial layer and the array of stabilization posts extends through a thickness of the sacrificial layer to support the array of micro devices.

2. The structure of claim 1, wherein the array of micro devices is an array of micro LED devices.

3. The structure of claim 1, further comprising an array of bottom conductive contacts on the bottom surfaces of the array of micro devices wherein the array of stabilization posts is bonded to the array of bottom contacts.

4. The structure of claim 3, wherein each micro device includes a corresponding bottom contact, and the corresponding plurality of stabilization posts is beneath the corresponding bottom contact.

5. A structure comprising:

a stabilization layer comprising an array of stabilization posts;

an array of micro devices on the array of stabilization posts, wherein each micro device comprises a bottom contact, and each bottom contact comprises a multiple layer stack;

wherein each micro device is supported by a corresponding plurality of stabilization posts of the array of stabilization posts that are underneath and bonded to a corresponding bottom contact, and each micro device includes a bottom surface that is wider than the corresponding plurality of stabilization posts.

6. The structure of claim 5, wherein the multiple layer stack includes a mirror layer.

7. The structure of claim 5, wherein the multiple layer stack comprises:

an electrode layer;

a mirror layer on the electrode layer;

a barrier layer on the mirror layer; and

a diffusion barrier layer on the electrode layer.

8. The structure of claim 7, wherein the electrode layer compress nickel.

9. The structure of claim 7, wherein the mirror layer comprises silver.

10. The structure of claim 7, wherein the barrier layer comprises titanium.

11. The structure of claim 7, wherein the diffusion barrier layer comprises platinum.

12. The structure of claim 7, wherein the multiple layer stack further comprises a bonding layer on the diffusion barrier layer.

13. The structure of claim 12, wherein the bonding layer comprises a noble metal.

14. The structure of claim 5, wherein the multiple layer stack comprises:

an electrode layer;

a mirror layer on the electrode layer; and

a barrier layer on the mirror layer;

wherein the barrier layer wraps around sidewalls of the electrode layer and the mirror layer.

15. The structure of claim 14, wherein the multiple layer stack further comprises a diffusion barrier layer on the electrode layer, wherein the diffusion barrier layer wraps around sidewalls of the electrode layer and the mirror layer.

16. The structure of claim 14, further comprising a bonding layer on the barrier layer.

17. The structure of claim 16, wherein the bonding layer comprises a noble metal.

18. The structure of claim 5, wherein the stabilization layer is bonded to a carrier substrate.

19. The structure of claim 18, wherein the carrier substrate comprises silicon.