Integrating a planar field effect transistor (FET) with a vertical FET
First Claim
1. A method comprising:
- manufacturing a semiconductor structure comprising a planar field-effect transistor (FET) and a vertical FET by integrating the planar FET into the vertical FET, wherein the integrating comprises;
masking a spacer in a planar region of the planar FET;
re-using the spacer as a gate dielectric for the planar region;
depositing gate metals; and
etching a vertical gate for a vertical region of the vertical FET and a planar gate for the planar region from the gate metals using a shared gate mask, wherein a top of the vertical gate and a top of the planar gate are co-planar.
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Abstract
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
29 Citations
8 Claims
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1. A method comprising:
manufacturing a semiconductor structure comprising a planar field-effect transistor (FET) and a vertical FET by integrating the planar FET into the vertical FET, wherein the integrating comprises; masking a spacer in a planar region of the planar FET; re-using the spacer as a gate dielectric for the planar region; depositing gate metals; and etching a vertical gate for a vertical region of the vertical FET and a planar gate for the planar region from the gate metals using a shared gate mask, wherein a top of the vertical gate and a top of the planar gate are co-planar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
Specification